drivers/gpu/drm/meson/meson_dw_mipi_dsi.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/meson/meson_dw_mipi_dsi.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/meson/meson_dw_mipi_dsi.h
Extension
.h
Size
6118 bytes
Lines
161
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __MESON_DW_MIPI_DSI_H
#define __MESON_DW_MIPI_DSI_H

/* Top-level registers */
/* [31: 4]    Reserved.     Default 0.
 *     [3] RW timing_rst_n: Default 1.
 *		1=Assert SW reset of timing feature.   0=Release reset.
 *     [2] RW dpi_rst_n: Default 1.
 *		1=Assert SW reset on mipi_dsi_host_dpi block.   0=Release reset.
 *     [1] RW intr_rst_n: Default 1.
 *		1=Assert SW reset on mipi_dsi_host_intr block.  0=Release reset.
 *     [0] RW dwc_rst_n:  Default 1.
 *		1=Assert SW reset on IP core.   0=Release reset.
 */
#define MIPI_DSI_TOP_SW_RESET                      0x3c0

#define MIPI_DSI_TOP_SW_RESET_DWC	BIT(0)
#define MIPI_DSI_TOP_SW_RESET_INTR	BIT(1)
#define MIPI_DSI_TOP_SW_RESET_DPI	BIT(2)
#define MIPI_DSI_TOP_SW_RESET_TIMING	BIT(3)

/* [31: 5] Reserved.   Default 0.
 *     [4] RW manual_edpihalt: Default 0.
 *		1=Manual suspend VencL; 0=do not suspend VencL.
 *     [3] RW auto_edpihalt_en: Default 0.
 *		1=Enable IP's edpihalt signal to suspend VencL;
 *		0=IP's edpihalt signal does not affect VencL.
 *     [2] RW clock_freerun: Apply to auto-clock gate only. Default 0.
 *		0=Default, use auto-clock gating to save power;
 *		1=use free-run clock, disable auto-clock gating, for debug mode.
 *     [1] RW enable_pixclk: A manual clock gate option, due to DWC IP does not
 *		have auto-clock gating. 1=Enable pixclk.      Default 0.
 *     [0] RW enable_sysclk: A manual clock gate option, due to DWC IP does not
 *		have auto-clock gating. 1=Enable sysclk.      Default 0.
 */
#define MIPI_DSI_TOP_CLK_CNTL                      0x3c4

#define MIPI_DSI_TOP_CLK_SYSCLK_EN	BIT(0)
#define MIPI_DSI_TOP_CLK_PIXCLK_EN	BIT(1)

/* [31:24]    Reserved. Default 0.
 * [23:20] RW dpi_color_mode: Define DPI pixel format. Default 0.
 *		0=16-bit RGB565 config 1;
 *		1=16-bit RGB565 config 2;
 *		2=16-bit RGB565 config 3;
 *		3=18-bit RGB666 config 1;
 *		4=18-bit RGB666 config 2;
 *		5=24-bit RGB888;
 *		6=20-bit YCbCr 4:2:2;
 *		7=24-bit YCbCr 4:2:2;
 *		8=16-bit YCbCr 4:2:2;
 *		9=30-bit RGB;
 *		10=36-bit RGB;
 *		11=12-bit YCbCr 4:2:0.
 *    [19] Reserved. Default 0.
 * [18:16] RW in_color_mode:  Define VENC data width. Default 0.
 *		0=30-bit pixel;
 *		1=24-bit pixel;
 *		2=18-bit pixel, RGB666;
 *		3=16-bit pixel, RGB565.
 * [15:14] RW chroma_subsample: Define method of chroma subsampling. Default 0.
 *		Applicable to YUV422 or YUV420 only.
 *		0=Use even pixel's chroma;
 *		1=Use odd pixel's chroma;
 *		2=Use averaged value between even and odd pair.
 * [13:12] RW comp2_sel:  Select which component to be Cr or B: Default 2.
 *		0=comp0; 1=comp1; 2=comp2.
 * [11:10] RW comp1_sel:  Select which component to be Cb or G: Default 1.
 *		0=comp0; 1=comp1; 2=comp2.
 *  [9: 8] RW comp0_sel:  Select which component to be Y  or R: Default 0.
 *		0=comp0; 1=comp1; 2=comp2.
 *     [7]    Reserved. Default 0.
 *     [6] RW de_pol:  Default 0.
 *		If DE input is active low, set to 1 to invert to active high.
 *     [5] RW hsync_pol: Default 0.
 *		If HS input is active low, set to 1 to invert to active high.
 *     [4] RW vsync_pol: Default 0.
 *		If VS input is active low, set to 1 to invert to active high.
 *     [3] RW dpicolorm: Signal to IP.   Default 0.
 *     [2] RW dpishutdn: Signal to IP.   Default 0.
 *     [1]    Reserved.  Default 0.
 *     [0]    Reserved.  Default 0.
 */
#define MIPI_DSI_TOP_CNTL                          0x3c8

/* VENC data width */
#define VENC_IN_COLOR_30B   0x0
#define VENC_IN_COLOR_24B   0x1
#define VENC_IN_COLOR_18B   0x2
#define VENC_IN_COLOR_16B   0x3

Annotation

Implementation Notes