drivers/gpu/drm/meson/meson_osd_afbcd.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/meson/meson_osd_afbcd.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/meson/meson_osd_afbcd.c
Extension
.c
Size
11217 bytes
Lines
403
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2019 BayLibre, SAS
 * Author: Neil Armstrong <narmstrong@baylibre.com>
 */

#include <linux/bitfield.h>

#include <drm/drm_print.h>
#include <drm/drm_fourcc.h>

#include "meson_drv.h"
#include "meson_registers.h"
#include "meson_viu.h"
#include "meson_rdma.h"
#include "meson_osd_afbcd.h"

/*
 * DOC: Driver for the ARM FrameBuffer Compression Decoders
 *
 * The Amlogic GXM and G12A SoC families embeds an AFBC Decoder,
 * to decode compressed buffers generated by the ARM Mali GPU.
 *
 * For the GXM Family, Amlogic designed their own Decoder, named in
 * the vendor source as "MESON_AFBC", and a single decoder is available
 * for the 2 OSD planes.
 * This decoder is compatible with the AFBC 1.0 specifications and the
 * Mali T820 GPU capabilities.
 * It supports :
 * - basic AFBC buffer for RGB32 only, thus YTR feature is mandatory
 * - SPARSE layout and SPLIT layout
 * - only 16x16 superblock
 *
 * The decoder reads the data from the SDRAM, decodes and sends the
 * decoded pixel stream to the OSD1 Plane pixel composer.
 *
 * For the G12A Family, Amlogic integrated an ARM AFBC Decoder, named
 * in the vendor source as "MALI_AFBC", and the decoder can decode up
 * to 4 surfaces, one for each of the 4 available OSDs.
 * This decoder is compatible with the AFBC 1.2 specifications for the
 * Mali G31 and G52 GPUs.
 * Is supports :
 * - basic AFBC buffer for multiple RGB and YUV pixel formats
 * - SPARSE layout and SPLIT layout
 * - 16x16 and 32x8 "wideblk" superblocks
 * - Tiled header
 *
 * The ARM AFBC Decoder independent from the VPU Pixel Pipeline, so
 * the ARM AFBC Decoder reads the data from the SDRAM then decodes
 * into a private internal physical address where the OSD1 Plane pixel
 * composer unpacks the decoded data.
 */

/* Amlogic AFBC Decoder for GXM Family */

#define OSD1_AFBCD_RGB32	0x15

static int meson_gxm_afbcd_pixel_fmt(u64 modifier, uint32_t format)
{
	switch (format) {
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
		return OSD1_AFBCD_RGB32;
	/* TOFIX support mode formats */
	default:
		DRM_DEBUG("unsupported afbc format[%08x]\n", format);
		return -EINVAL;
	}
}

static bool meson_gxm_afbcd_supported_fmt(u64 modifier, uint32_t format)
{
	if (modifier & AFBC_FORMAT_MOD_BLOCK_SIZE_32x8)
		return false;

	if (!(modifier & AFBC_FORMAT_MOD_YTR))
		return false;

	return meson_gxm_afbcd_pixel_fmt(modifier, format) >= 0;
}

static int meson_gxm_afbcd_reset(struct meson_drm *priv)
{
	writel_relaxed(VIU_SW_RESET_OSD1_AFBCD,
		       priv->io_base + _REG(VIU_SW_RESET));
	writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET));

	return 0;
}

Annotation

Implementation Notes