drivers/gpu/drm/meson/meson_vclk.c

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/meson/meson_vclk.c

Extension

.c

Size

32955 bytes

Lines

1132

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: exported/initcall integration point

Status

integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/export.h
• drm/drm_print.h
• meson_drv.h
• meson_vclk.h

Detected Declarations

• struct meson_vclk_params
• function meson_vid_pll_set
• function meson_venci_cvbs_clock_config
• function meson_vpu_is_compatible
• function pll_od_to_reg
• function meson_hdmi_pll_set_params
• function meson_vpu_is_compatible
• function meson_hdmi_pll_get_m
• function meson_hdmi_pll_get_frac
• function meson_hdmi_pll_validate_params
• function meson_vpu_is_compatible
• function meson_hdmi_pll_find_params
• function meson_vclk_dmt_supported_freq
• function meson_hdmi_pll_generic_set
• function meson_vclk_freqs_are_matching_param
• function meson_vclk_vic_supported_freq
• function meson_vclk_set
• function meson_vpu_is_compatible
• function meson_vclk_setup
• export meson_vclk_dmt_supported_freq
• export meson_vclk_vic_supported_freq
• export meson_vclk_setup

Annotated Snippet

struct meson_vclk_params {
	unsigned long long pll_freq;
	unsigned long long phy_freq;
	unsigned long long vclk_freq;
	unsigned long long venc_freq;
	unsigned long long pixel_freq;
	unsigned int pll_od1;
	unsigned int pll_od2;
	unsigned int pll_od3;
	unsigned int vid_pll_div;
	unsigned int vclk_div;
} params[] = {
	[MESON_VCLK_HDMI_ENCI_54000] = {
		.pll_freq = 4320000000,
		.phy_freq = 270000000,
		.vclk_freq = 54000000,
		.venc_freq = 54000000,
		.pixel_freq = 54000000,
		.pll_od1 = 4,
		.pll_od2 = 4,
		.pll_od3 = 1,
		.vid_pll_div = VID_PLL_DIV_5,
		.vclk_div = 1,
	},
	[MESON_VCLK_HDMI_DDR_54000] = {
		.pll_freq = 4320000000,
		.phy_freq = 270000000,
		.vclk_freq = 54000000,
		.venc_freq = 54000000,
		.pixel_freq = 27000000,
		.pll_od1 = 4,
		.pll_od2 = 4,
		.pll_od3 = 1,
		.vid_pll_div = VID_PLL_DIV_5,
		.vclk_div = 1,
	},
	[MESON_VCLK_HDMI_DDR_148500] = {
		.pll_freq = 2970000000,
		.phy_freq = 742500000,
		.vclk_freq = 148500000,
		.venc_freq = 148500000,
		.pixel_freq = 74250000,
		.pll_od1 = 4,
		.pll_od2 = 1,
		.pll_od3 = 1,
		.vid_pll_div = VID_PLL_DIV_5,
		.vclk_div = 1,
	},
	[MESON_VCLK_HDMI_74250] = {
		.pll_freq = 2970000000,
		.phy_freq = 742500000,
		.vclk_freq = 74250000,
		.venc_freq = 74250000,
		.pixel_freq = 74250000,
		.pll_od1 = 2,
		.pll_od2 = 2,
		.pll_od3 = 2,
		.vid_pll_div = VID_PLL_DIV_5,
		.vclk_div = 1,
	},
	[MESON_VCLK_HDMI_148500] = {
		.pll_freq = 2970000000,
		.phy_freq = 1485000000,
		.vclk_freq = 148500000,
		.venc_freq = 148500000,
		.pixel_freq = 148500000,
		.pll_od1 = 1,
		.pll_od2 = 2,
		.pll_od3 = 2,
		.vid_pll_div = VID_PLL_DIV_5,
		.vclk_div = 1,
	},
	[MESON_VCLK_HDMI_297000] = {
		.pll_freq = 5940000000,
		.phy_freq = 2970000000,
		.venc_freq = 297000000,
		.vclk_freq = 297000000,
		.pixel_freq = 297000000,
		.pll_od1 = 2,
		.pll_od2 = 1,
		.pll_od3 = 1,
		.vid_pll_div = VID_PLL_DIV_5,
		.vclk_div = 2,
	},
	[MESON_VCLK_HDMI_594000] = {
		.pll_freq = 5940000000,
		.phy_freq = 5940000000,
		.venc_freq = 594000000,
		.vclk_freq = 594000000,
		.pixel_freq = 594000000,

Annotation

• Immediate include surface: `linux/export.h`, `drm/drm_print.h`, `meson_drv.h`, `meson_vclk.h`.
• Detected declarations: `struct meson_vclk_params`, `function meson_vid_pll_set`, `function meson_venci_cvbs_clock_config`, `function meson_vpu_is_compatible`, `function pll_od_to_reg`, `function meson_hdmi_pll_set_params`, `function meson_vpu_is_compatible`, `function meson_hdmi_pll_get_m`, `function meson_hdmi_pll_get_frac`, `function meson_hdmi_pll_validate_params`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: integration implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.