drivers/gpu/drm/msm/adreno/a6xx_gmu.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/adreno/a6xx_gmu.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
Extension
.h
Size
6500 bytes
Lines
245
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct a6xx_gmu_bo {
	struct drm_gem_object *obj;
	void *virt;
	size_t size;
	u64 iova;
};

#define GMU_MAX_GX_FREQS	32
#define GMU_MAX_CX_FREQS	6
#define GMU_MAX_BCMS		3

struct a6xx_bcm {
	char *name;
	unsigned int buswidth;
	bool fixed;
	unsigned int perfmode;
	unsigned int perfmode_bw;
};

/*
 * These define the different GMU wake up options - these define how both the
 * CPU and the GMU bring up the hardware
 */

/* THe GMU has already been booted and the rentention registers are active */
#define GMU_WARM_BOOT 0

/* the GMU is coming up for the first time or back from a power collapse */
#define GMU_COLD_BOOT 1

/*
 * These define the level of control that the GMU has - the higher the number
 * the more things that the GMU hardware controls on its own.
 */

/* The GMU does not do any idle state management */
#define GMU_IDLE_STATE_ACTIVE 0

/* Unknown power state. Not exposed by the firmware. For documentation purpose only */
#define GMU_IDLE_STATE_RESERVED 1

/* The GMU manages SPTP power collapse */
#define GMU_IDLE_STATE_SPTP 2

/* The GMU does automatic IFPC (intra-frame power collapse) */
#define GMU_IDLE_STATE_IFPC 3

struct a6xx_gmu {
	struct device *dev;

	/* For serializing communication with the GMU: */
	struct mutex lock;

	struct drm_gpuvm *vm;

	void __iomem *mmio;
	u32 mmio_offset;
	void __iomem *rscc;

	int hfi_irq;
	int gmu_irq;

	struct device *gxpd;
	struct device *cxpd;

	int idle_level;

	struct a6xx_gmu_bo hfi;
	struct a6xx_gmu_bo debug;
	struct a6xx_gmu_bo icache;
	struct a6xx_gmu_bo dcache;
	struct a6xx_gmu_bo dummy;
	struct a6xx_gmu_bo log;

	int nr_clocks;
	struct clk_bulk_data *clocks;
	struct clk *core_clk;
	struct clk *hub_clk;

	/* current performance index set externally */
	int current_perf_index;

	int nr_gpu_freqs;
	unsigned long gpu_freqs[GMU_MAX_GX_FREQS];
	u32 gx_arc_votes[GMU_MAX_GX_FREQS];
	u32 dep_arc_votes[GMU_MAX_GX_FREQS];
	struct a6xx_hfi_acd_table acd_table;

	int nr_gpu_bws;
	unsigned long gpu_bw_table[GMU_MAX_GX_FREQS];

Annotation

Implementation Notes