drivers/gpu/drm/msm/adreno/a6xx_gpu.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/adreno/a6xx_gpu.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
Extension
.h
Size
10914 bytes
Lines
350
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cpu_gpu_lock {
	uint32_t gpu_req;
	uint32_t cpu_req;
	uint32_t turn;
	union {
		/* a6xx: */
		struct {
			uint16_t list_length;
			uint16_t list_offset;
		};
		/* a7xx+: */
		struct {
			uint8_t ifpc_list_len;
			uint8_t preemption_list_len;
			uint16_t dynamic_list_len;
		};
	};
	uint64_t regs[];
};

/**
 * struct a6xx_info - a6xx specific information from device table
 *
 * @hwcg: hw clock gating register sequence
 * @protect: CP_PROTECT settings
 * @pwrup_reglist pwrup reglist for preemption
 */
struct a6xx_info {
	const struct adreno_reglist *hwcg;
	const struct adreno_protect *protect;
	const struct adreno_reglist_list *pwrup_reglist;
	const struct adreno_reglist_pipe_list *dyn_pwrup_reglist;
	const struct adreno_reglist_list *ifpc_reglist;
	const struct adreno_reglist *gbif_cx;
	const struct adreno_reglist_pipe *nonctxt_reglist;
	u32 max_slices;
	u32 gmu_chipid;
	u32 gmu_cgc_mode;
	u32 prim_fifo_threshold;
	const struct a6xx_bcm *bcms;
};

struct a6xx_gpu {
	struct adreno_gpu base;

	struct drm_gem_object *sqe_bo;
	uint64_t sqe_iova;
	struct drm_gem_object *aqe_bo;
	uint64_t aqe_iova;

	struct msm_ringbuffer *cur_ring;
	struct msm_ringbuffer *next_ring;

	struct drm_gem_object *preempt_bo[MSM_GPU_MAX_RINGS];
	void *preempt[MSM_GPU_MAX_RINGS];
	uint64_t preempt_iova[MSM_GPU_MAX_RINGS];
	struct drm_gem_object *preempt_smmu_bo[MSM_GPU_MAX_RINGS];
	void *preempt_smmu[MSM_GPU_MAX_RINGS];
	uint64_t preempt_smmu_iova[MSM_GPU_MAX_RINGS];
	uint32_t last_seqno[MSM_GPU_MAX_RINGS];

	atomic_t preempt_state;
	spinlock_t eval_lock;
	struct timer_list preempt_timer;

	unsigned int preempt_level;
	bool uses_gmem;
	bool skip_save_restore;

	struct drm_gem_object *preempt_postamble_bo;
	void *preempt_postamble_ptr;
	uint64_t preempt_postamble_iova;
	uint64_t preempt_postamble_len;
	bool postamble_enabled;

	struct a6xx_gmu gmu;

	struct drm_gem_object *shadow_bo;
	uint64_t shadow_iova;
	uint32_t *shadow;

	struct drm_gem_object *pwrup_reglist_bo;
#define PWRUP_REGLIST_SIZE (2 * PAGE_SIZE)
	void *pwrup_reglist_ptr;
	uint64_t pwrup_reglist_iova;
	bool pwrup_reglist_emitted;

	/*
	 * Offset of start of SEL regs appended to pwrup_reglist.  This
	 * is equal to lock->dynamic_list_len if no SEL regs are appended

Annotation

Implementation Notes