drivers/gpu/drm/msm/adreno/a6xx_hfi.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/adreno/a6xx_hfi.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/adreno/a6xx_hfi.h
Extension
.h
Size
7262 bytes
Lines
339
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct a6xx_hfi_queue_table_header {
	u32 version;
	u32 size;		/* Size of the queue table in dwords */
	u32 qhdr0_offset;	/* Offset of the first queue header */
	u32 qhdr_size;		/* Size of the queue headers */
	u32 num_queues;		/* Number of total queues */
	u32 active_queues;	/* Number of active queues */
} __packed;

struct a6xx_hfi_queue_header {
	u32 status;
	u32 iova;
	u32 type;
	u32 size;
	u32 msg_size;
	u32 dropped;
	u32 rx_watermark;
	u32 tx_watermark;
	u32 rx_request;
	u32 tx_request;
	u32 read_index;
	u32 write_index;
} __packed;

struct a6xx_hfi_queue {
	struct a6xx_hfi_queue_header *header;
	spinlock_t lock;
	u32 *data;
	atomic_t seqnum;

	/*
	 * Tracking for the start index of the last N messages in the
	 * queue, for the benefit of devcore dump / crashdec (since
	 * parsing in the reverse direction to decode the last N
	 * messages is difficult to do and would rely on heuristics
	 * which are not guaranteed to be correct)
	 */
#define HFI_HISTORY_SZ 8
	s32 history[HFI_HISTORY_SZ];
	u8  history_idx;
};

/* This is the outgoing queue to the GMU */
#define HFI_COMMAND_QUEUE 0

/* THis is the incoming response queue from the GMU */
#define HFI_RESPONSE_QUEUE 1

#define HFI_HEADER_ID(msg) ((msg) & 0xff)
#define HFI_HEADER_SIZE(msg) (((msg) >> 8) & 0xff)
#define HFI_HEADER_SEQNUM(msg) (((msg) >> 20) & 0xfff)

/* FIXME: Do we need this or can we use ARRAY_SIZE? */
#define HFI_RESPONSE_PAYLOAD_SIZE 16

/* HFI message types */

#define HFI_MSG_CMD 0
#define HFI_MSG_ACK 1
#define HFI_MSG_ACK_V1 2

#define HFI_F2H_MSG_ACK 126

struct a6xx_hfi_msg_response {
	u32 header;
	u32 ret_header;
	u32 error;
	u32 payload[HFI_RESPONSE_PAYLOAD_SIZE];
} __packed;

#define HFI_F2H_MSG_ERROR 100

struct a6xx_hfi_msg_error {
	u32 header;
	u32 code;
	u32 payload[2];
} __packed;

#define HFI_H2F_MSG_INIT 0

struct a6xx_hfi_msg_gmu_init_cmd {
	u32 header;
	u32 seg_id;
	u32 dbg_buffer_addr;
	u32 dbg_buffer_size;
	u32 boot_state;
} __packed;

#define HFI_H2F_MSG_FW_VERSION 1

Annotation

Implementation Notes