drivers/gpu/drm/msm/adreno/a8xx_gpu.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/adreno/a8xx_gpu.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
Extension
.c
Size
41714 bytes
Lines
1370
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (protect->regs[i]) {
			gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]);
			final_cfg = protect->regs[i];
		}
	}

	/*
	 * Last span feature is only supported on PIPE specific register.
	 * So update those here
	 */
	a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg);
	a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg);

	a8xx_aperture_clear(gpu);
}

static void a8xx_set_ubwc_config(struct msm_gpu *gpu)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config;
	u32 level2_swizzling_dis = !(qcom_ubwc_swizzle(cfg) & UBWC_SWIZZLE_ENABLE_LVL2);
	u32 level3_swizzling_dis = !(qcom_ubwc_swizzle(cfg) & UBWC_SWIZZLE_ENABLE_LVL3);
	bool rgba8888_lossless = false, fp16compoptdis = false;
	bool yuvnotcomptofc = false, min_acc_len_64b = false;
	bool rgb565_predicator = false;
	bool amsbc = qcom_ubwc_enable_amsbc(cfg);
	bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);
	u32 ubwc_version = cfg->ubwc_enc_version;
	u32 hbb, hbb_hi, hbb_lo, mode;
	u8 uavflagprd_inv = 2;

	if (ubwc_version > UBWC_6_0)
		dev_err(&gpu->pdev->dev, "Unknown UBWC version: 0x%x\n", ubwc_version);

	if (ubwc_version == UBWC_6_0)
		yuvnotcomptofc = true;

	if (ubwc_version < UBWC_5_0 &&
	    ubwc_version >= UBWC_4_0)
		rgba8888_lossless = true;

	if (ubwc_version < UBWC_4_3)
		fp16compoptdis = true;

	if (cfg->ubwc_enc_version >= UBWC_4_0)
		rgb565_predicator = true;

	if (ubwc_version < UBWC_3_0)
		dev_err(&gpu->pdev->dev, "Unsupported UBWC version: 0x%x\n", ubwc_version);

	mode = qcom_ubwc_version_tag(cfg);

	/*
	 * We subtract 13 from the highest bank bit (13 is the minimum value
	 * allowed by hw) and write the lowest two bits of the remaining value
	 * as hbb_lo and the one above it as hbb_hi to the hardware.
	 */
	WARN_ON(cfg->highest_bank_bit < 13);
	hbb = cfg->highest_bank_bit - 13;
	hbb_hi = hbb >> 2;
	hbb_lo = hbb & 3;

	a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_GRAS_NC_MODE_CNTL,
			hbb << 5 |
			level3_swizzling_dis << 4 |
			level2_swizzling_dis << 3);

	a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_GRAS_NC_MODE_CNTL,
			hbb << 5 |
			level3_swizzling_dis << 4 |
			level2_swizzling_dis << 3);

	a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_CCU_NC_MODE_CNTL,
			yuvnotcomptofc << 6 |
			level3_swizzling_dis << 5 |
			level2_swizzling_dis << 4 |
			hbb_hi << 3 |
			hbb_lo << 1);

	a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_CMP_NC_MODE_CNTL,
			mode << 15 |
			yuvnotcomptofc << 6 |
			rgba8888_lossless << 4 |
			fp16compoptdis << 3 |
			rgb565_predicator << 2 |
			amsbc << 1 |
			min_acc_len_64b);

	a8xx_aperture_clear(gpu);

Annotation

Implementation Notes