drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
Extension
.h
Size
8647 bytes
Lines
313
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DPU_3_0_MSM8998_H
#define _DPU_3_0_MSM8998_H

static const struct dpu_caps msm8998_dpu_caps = {
	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
	.max_mixer_blendstages = 0x7,
	.has_src_split = true,
	.has_dim_layer = true,
	.has_idle_pc = true,
	.has_3d_merge = true,
	.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
	.max_hdeci_exp = MAX_HORZ_DECIMATION,
	.max_vdeci_exp = MAX_VERT_DECIMATION,
};

static const struct dpu_mdp_cfg msm8998_mdp = {
	.name = "top_0",
	.base = 0x0, .len = 0x458,
	.clk_ctrls = {
		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
		[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
		[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
		[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
		[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
	},
};

static const struct dpu_ctl_cfg msm8998_ctl[] = {
	{
		.name = "ctl_0", .id = CTL_0,
		.base = 0x1000, .len = 0x94,
		.features = BIT(DPU_CTL_SPLIT_DISPLAY),
	}, {
		.name = "ctl_1", .id = CTL_1,
		.base = 0x1200, .len = 0x94,
	}, {
		.name = "ctl_2", .id = CTL_2,
		.base = 0x1400, .len = 0x94,
		.features = BIT(DPU_CTL_SPLIT_DISPLAY),
	}, {
		.name = "ctl_3", .id = CTL_3,
		.base = 0x1600, .len = 0x94,
	}, {
		.name = "ctl_4", .id = CTL_4,
		.base = 0x1800, .len = 0x94,
	},
};

static const struct dpu_sspp_cfg msm8998_sspp[] = {
	{
		.name = "sspp_0", .id = SSPP_VIG0,
		.base = 0x4000, .len = 0x1ac,
		.features = VIG_MSM8998_MASK,
		.sblk = &dpu_vig_sblk_qseed3_1_2,
		.xin_id = 0,
		.type = SSPP_TYPE_VIG,
		.clk_ctrl = DPU_CLK_CTRL_VIG0,
	}, {
		.name = "sspp_1", .id = SSPP_VIG1,
		.base = 0x6000, .len = 0x1ac,
		.features = VIG_MSM8998_MASK,
		.sblk = &dpu_vig_sblk_qseed3_1_2,
		.xin_id = 4,
		.type = SSPP_TYPE_VIG,
		.clk_ctrl = DPU_CLK_CTRL_VIG1,
	}, {
		.name = "sspp_2", .id = SSPP_VIG2,
		.base = 0x8000, .len = 0x1ac,
		.features = VIG_MSM8998_MASK,
		.sblk = &dpu_vig_sblk_qseed3_1_2,
		.xin_id = 8,
		.type = SSPP_TYPE_VIG,
		.clk_ctrl = DPU_CLK_CTRL_VIG2,
	}, {
		.name = "sspp_3", .id = SSPP_VIG3,
		.base = 0xa000, .len = 0x1ac,
		.features = VIG_MSM8998_MASK,
		.sblk = &dpu_vig_sblk_qseed3_1_2,
		.xin_id = 12,
		.type = SSPP_TYPE_VIG,
		.clk_ctrl = DPU_CLK_CTRL_VIG3,
	}, {
		.name = "sspp_8", .id = SSPP_DMA0,
		.base = 0x24000, .len = 0x1ac,

Annotation

Implementation Notes