drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
Extension
.c
Size
23079 bytes
Lines
785
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (!phys_enc->hw_pp) {
			DPU_ERROR("invalid encoder\n");
			return;
		}

		DRM_DEBUG_KMS("id:%u pp:%d state:%d\n", DRMID(phys_enc->parent),
			      phys_enc->hw_pp->idx - PINGPONG_0,
			      phys_enc->enable_state);

		if (phys_enc->hw_pp->ops.disable_tearcheck)
			phys_enc->hw_pp->ops.disable_tearcheck(phys_enc->hw_pp);
	}

	if (phys_enc->hw_intf->ops.bind_pingpong_blk) {
		phys_enc->hw_intf->ops.bind_pingpong_blk(
				phys_enc->hw_intf,
				PINGPONG_NONE);

		ctl = phys_enc->hw_ctl;
		ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
	}

	phys_enc->enable_state = DPU_ENC_DISABLED;
}

static void dpu_encoder_phys_cmd_prepare_for_kickoff(
		struct dpu_encoder_phys *phys_enc)
{
	struct dpu_encoder_phys_cmd *cmd_enc =
			to_dpu_encoder_phys_cmd(phys_enc);
	int ret;

	if (!phys_enc->hw_pp) {
		DPU_ERROR("invalid encoder\n");
		return;
	}
	DRM_DEBUG_KMS("id:%u pp:%d pending_cnt:%d\n", DRMID(phys_enc->parent),
		      phys_enc->hw_pp->idx - PINGPONG_0,
		      atomic_read(&phys_enc->pending_kickoff_cnt));

	/*
	 * Mark kickoff request as outstanding. If there are more than one,
	 * outstanding, then we have to wait for the previous one to complete
	 */
	ret = _dpu_encoder_phys_cmd_wait_for_idle(phys_enc);
	if (ret) {
		/* force pending_kickoff_cnt 0 to discard failed kickoff */
		atomic_set(&phys_enc->pending_kickoff_cnt, 0);
		DRM_ERROR("failed wait_for_idle: id:%u ret:%d pp:%d\n",
			  DRMID(phys_enc->parent), ret,
			  phys_enc->hw_pp->idx - PINGPONG_0);
	}

	dpu_encoder_phys_cmd_enable_te(phys_enc);

	DPU_DEBUG_CMDENC(cmd_enc, "pp:%d pending_cnt %d\n",
			phys_enc->hw_pp->idx - PINGPONG_0,
			atomic_read(&phys_enc->pending_kickoff_cnt));
}

static void dpu_encoder_phys_cmd_enable_te(struct dpu_encoder_phys *phys_enc)
{
	if (!phys_enc)
		return;
	if (!dpu_encoder_phys_cmd_is_master(phys_enc))
		return;

	if (phys_enc->has_intf_te) {
		if (!phys_enc->hw_intf->ops.disable_autorefresh)
			return;

		phys_enc->hw_intf->ops.disable_autorefresh(
				phys_enc->hw_intf,
				DRMID(phys_enc->parent),
				phys_enc->cached_mode.vdisplay);
	} else {
		if (!phys_enc->hw_pp ||
		    !phys_enc->hw_pp->ops.disable_autorefresh)
			return;

		phys_enc->hw_pp->ops.disable_autorefresh(
				phys_enc->hw_pp,
				DRMID(phys_enc->parent),
				phys_enc->cached_mode.vdisplay);
	}
}

static int _dpu_encoder_phys_cmd_wait_for_ctl_start(
		struct dpu_encoder_phys *phys_enc)
{

Annotation

Implementation Notes