drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c- Extension
.c- Size
- 19655 bytes
- Lines
- 695
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/debugfs.hdrm/drm_framebuffer.hdrm/drm_managed.hdpu_encoder_phys.hdpu_formats.hdpu_hw_top.hdpu_hw_wb.hdpu_hw_lm.hdpu_hw_merge3d.hdpu_hw_interrupts.hdpu_core_irq.hdpu_vbif.hdpu_crtc.hdisp/msm_disp_snapshot.h
Detected Declarations
function Copyrightfunction _dpu_encoder_phys_wb_clk_force_ctrlfunction dpu_encoder_phys_wb_set_ot_limitfunction dpu_encoder_phys_wb_set_qos_remapfunction dpu_encoder_phys_wb_set_qosfunction dpu_encoder_phys_wb_setup_fbfunction dpu_encoder_phys_wb_setup_ctlfunction _dpu_encoder_phys_wb_update_flushfunction dpu_encoder_phys_wb_setupfunction dpu_encoder_phys_wb_done_irqfunction dpu_encoder_phys_wb_irq_enablefunction dpu_encoder_phys_wb_irq_disablefunction dpu_encoder_phys_wb_atomic_mode_setfunction _dpu_encoder_phys_wb_handle_wbdone_timeoutfunction dpu_encoder_phys_wb_wait_for_commit_donefunction dpu_encoder_phys_wb_prepare_for_kickofffunction dpu_encoder_phys_wb_needs_single_flushfunction dpu_encoder_phys_wb_handle_post_kickofffunction dpu_encoder_phys_wb_enablefunction dpu_encoder_phys_wb_disablefunction dpu_encoder_phys_wb_prepare_wb_jobfunction dpu_encoder_phys_wb_cleanup_wb_jobfunction dpu_encoder_phys_wb_is_valid_for_commitfunction dpu_encoder_phys_wb_init_ops
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
#include <linux/debugfs.h>
#include <drm/drm_framebuffer.h>
#include <drm/drm_managed.h>
#include "dpu_encoder_phys.h"
#include "dpu_formats.h"
#include "dpu_hw_top.h"
#include "dpu_hw_wb.h"
#include "dpu_hw_lm.h"
#include "dpu_hw_merge3d.h"
#include "dpu_hw_interrupts.h"
#include "dpu_core_irq.h"
#include "dpu_vbif.h"
#include "dpu_crtc.h"
#include "disp/msm_disp_snapshot.h"
#define to_dpu_encoder_phys_wb(x) \
container_of(x, struct dpu_encoder_phys_wb, base)
/**
* dpu_encoder_phys_wb_is_master - report wb always as master encoder
* @phys_enc: Pointer to physical encoder
*/
static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc)
{
/* there is only one physical enc for dpu_writeback */
return true;
}
static bool _dpu_encoder_phys_wb_clk_force_ctrl(struct dpu_hw_wb *wb,
struct dpu_hw_mdp *mdp,
bool enable, bool *forced_on)
{
if (wb->ops.setup_clk_force_ctrl) {
*forced_on = wb->ops.setup_clk_force_ctrl(wb, enable);
return true;
}
if (mdp->ops.setup_clk_force_ctrl) {
*forced_on = mdp->ops.setup_clk_force_ctrl(mdp, wb->caps->clk_ctrl, enable);
return true;
}
return false;
}
/**
* dpu_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
* @phys_enc: Pointer to physical encoder
*/
static void dpu_encoder_phys_wb_set_ot_limit(
struct dpu_encoder_phys *phys_enc)
{
struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
struct dpu_vbif_set_ot_params ot_params;
bool forced_on = false;
memset(&ot_params, 0, sizeof(ot_params));
ot_params.xin_id = hw_wb->caps->xin_id;
ot_params.num = hw_wb->idx - WB_0;
ot_params.width = phys_enc->cached_mode.hdisplay;
ot_params.height = phys_enc->cached_mode.vdisplay;
ot_params.is_wfd = !dpu_encoder_helper_get_cwb_mask(phys_enc);
ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
/* XXX: WB on MSM8996 should use VBIF_NRT */
ot_params.rd = false;
if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
true, &forced_on))
return;
dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params);
if (forced_on)
_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
false, &forced_on);
}
/**
* dpu_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback
* @phys_enc: Pointer to physical encoder
*/
Annotation
- Immediate include surface: `linux/debugfs.h`, `drm/drm_framebuffer.h`, `drm/drm_managed.h`, `dpu_encoder_phys.h`, `dpu_formats.h`, `dpu_hw_top.h`, `dpu_hw_wb.h`, `dpu_hw_lm.h`.
- Detected declarations: `function Copyright`, `function _dpu_encoder_phys_wb_clk_force_ctrl`, `function dpu_encoder_phys_wb_set_ot_limit`, `function dpu_encoder_phys_wb_set_qos_remap`, `function dpu_encoder_phys_wb_set_qos`, `function dpu_encoder_phys_wb_setup_fb`, `function dpu_encoder_phys_wb_setup_ctl`, `function _dpu_encoder_phys_wb_update_flush`, `function dpu_encoder_phys_wb_setup`, `function dpu_encoder_phys_wb_done_irq`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.