drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
Extension
.c
Size
5883 bytes
Lines
217
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2020-2022, Linaro Limited
 */

#include <drm/drm_managed.h>

#include <drm/display/drm_dsc_helper.h>

#include "dpu_kms.h"
#include "dpu_hw_catalog.h"
#include "dpu_hwio.h"
#include "dpu_hw_mdss.h"
#include "dpu_hw_dsc.h"

#define DSC_COMMON_MODE                 0x000
#define DSC_ENC                         0x004
#define DSC_PICTURE                     0x008
#define DSC_SLICE                       0x00C
#define DSC_CHUNK_SIZE                  0x010
#define DSC_DELAY                       0x014
#define DSC_SCALE_INITIAL               0x018
#define DSC_SCALE_DEC_INTERVAL          0x01C
#define DSC_SCALE_INC_INTERVAL          0x020
#define DSC_FIRST_LINE_BPG_OFFSET       0x024
#define DSC_BPG_OFFSET                  0x028
#define DSC_DSC_OFFSET                  0x02C
#define DSC_FLATNESS                    0x030
#define DSC_RC_MODEL_SIZE               0x034
#define DSC_RC                          0x038
#define DSC_RC_BUF_THRESH               0x03C
#define DSC_RANGE_MIN_QP                0x074
#define DSC_RANGE_MAX_QP                0x0B0
#define DSC_RANGE_BPG_OFFSET            0x0EC

#define DSC_CTL(m) (0x1800 - 0x3FC * (m - DSC_0))

static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
{
	struct dpu_hw_blk_reg_map *c = &dsc->hw;

	DPU_REG_WRITE(c, DSC_COMMON_MODE, 0);
}

static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
			      struct drm_dsc_config *dsc,
			      u32 mode,
			      u32 initial_lines)
{
	struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
	u32 data;
	u32 slice_last_group_size;
	u32 det_thresh_flatness;
	bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
	bool input_10_bits = dsc->bits_per_component == 10;

	DPU_REG_WRITE(c, DSC_COMMON_MODE, mode);

	if (is_cmd_mode)
		initial_lines += 1;

	slice_last_group_size = (dsc->slice_width + 2) % 3;

	data = (initial_lines << 20);
	data |= (slice_last_group_size << 18);
	/* bpp is 6.4 format, 4 LSBs bits are for fractional part */
	data |= (dsc->bits_per_pixel << 8);
	data |= (dsc->block_pred_enable << 7);
	data |= (dsc->line_buf_depth << 3);
	data |= (dsc->simple_422 << 2);
	data |= (dsc->convert_rgb << 1);
	data |= input_10_bits;

	DPU_REG_WRITE(c, DSC_ENC, data);

	data = dsc->pic_width << 16;
	data |= dsc->pic_height;
	DPU_REG_WRITE(c, DSC_PICTURE, data);

	data = dsc->slice_width << 16;
	data |= dsc->slice_height;
	DPU_REG_WRITE(c, DSC_SLICE, data);

	data = dsc->slice_chunk_size << 16;
	DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);

	data = dsc->initial_dec_delay << 16;
	data |= dsc->initial_xmit_delay;
	DPU_REG_WRITE(c, DSC_DELAY, data);

Annotation

Implementation Notes