drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
Extension
.c
Size
11037 bytes
Lines
398
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (pipe >= SSPP_DMA0 && pipe <= SSPP_DMA5) {
			pipe_type = 0;
			pipe_id = pipe - SSPP_DMA0;
		} else if (pipe >= SSPP_VIG0 && pipe <= SSPP_VIG3) {
			pipe_type = 1;
			pipe_id = pipe - SSPP_VIG0;
		} else {
			DPU_ERROR("invalid rec-%d pipe:%d\n", i, pipe);
			return -EINVAL;
		}

		/* translate rec data to SWI rec_id */
		if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) {
			rec_id = 0;
		} else if (rect_index == DPU_SSPP_RECT_1) {
			rec_id = 1;
		} else {
			DPU_ERROR("invalid rec-%d rect_index:%d\n", i, rect_index);
			rec_id = 0;
		}

		/* calculate SWI value for rec-0 and rec-1 and store it temporary buffer */
		src_sel[i] = (((pipe_type & 0x3) << 6) | ((rec_id & 0x3) << 4) | (pipe_id & 0xf));
	}

	/* calculate final SWI register value for rec-0 and rec-1 */
	*value = 0;
	for (i = 0; i < pipes_per_stage; i++)
		*value |= src_sel[i] << (i * 8);

	return 0;
}

static int dpu_hw_lm_setup_blendstage(struct dpu_hw_mixer *ctx, enum dpu_lm lm,
				      struct dpu_hw_stage_cfg *stage_cfg)
{
	struct dpu_hw_blk_reg_map *c = &ctx->hw;
	int i, ret, stages, stage_off, pipes_per_stage;
	u32 value;

	stages = ctx->cap->sblk->maxblendstages;
	if (stages <= 0)
		return -EINVAL;

	if (test_bit(DPU_MIXER_SOURCESPLIT, &ctx->cap->features))
		pipes_per_stage = PIPES_PER_STAGE;
	else
		pipes_per_stage = 1;

	/*
	 * When stage configuration is empty, we can enable the
	 * border color by setting the corresponding LAYER_ACTIVE bit
	 * and un-staging all the pipes from the layer mixer.
	 */
	if (!stage_cfg)
		DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE);

	for (i = DPU_STAGE_0; i <= stages; i++) {
		stage_off = _stage_offset(ctx, i);
		if (stage_off < 0)
			return stage_off;

		ret = _set_staged_sspp(i, stage_cfg, pipes_per_stage, &value);
		if (ret)
			return ret;

		DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off, value);
	}

	return 0;
}

static int dpu_hw_lm_clear_all_blendstages(struct dpu_hw_mixer *ctx)
{
	struct dpu_hw_blk_reg_map *c = &ctx->hw;
	int i, stages, stage_off;

	stages = ctx->cap->sblk->maxblendstages;
	if (stages <= 0)
		return -EINVAL;

	DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE);

	for (i = DPU_STAGE_0; i <= stages; i++) {
		stage_off = _stage_offset(ctx, i);
		if (stage_off < 0)
			return stage_off;

		DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off,
			      LM_BG_SRC_SEL_V12_RESET_VALUE);

Annotation

Implementation Notes