drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h- Extension
.h- Size
- 3337 bytes
- Lines
- 127
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dpu_hw_catalog.hdpu_hw_mdss.hdpu_hw_util.h
Detected Declarations
struct dpu_hw_pingpongstruct dpu_hw_dither_cfgstruct dpu_hw_pingpong_opsstruct dpu_hw_merge_3dstruct dpu_hw_pingpong
Annotated Snippet
struct dpu_hw_dither_cfg {
u64 flags;
u32 temporal_en;
u32 c0_bitdepth;
u32 c1_bitdepth;
u32 c2_bitdepth;
u32 c3_bitdepth;
u32 matrix[DITHER_MATRIX_SZ];
};
/**
* struct dpu_hw_pingpong_ops : Interface to the pingpong Hw driver functions
* Assumption is these functions will be called after clocks are enabled
* @enable_tearcheck: program and enable tear check block
* @disable_tearcheck: disable able tear check block
* @setup_dither : function to program the dither hw block
* @get_line_count: obtain current vertical line counter
*/
struct dpu_hw_pingpong_ops {
/**
* @enable_tearcheck: enables vysnc generation and sets up init value of
* read pointer and programs the tear check cofiguration
*/
int (*enable_tearcheck)(struct dpu_hw_pingpong *pp,
struct dpu_hw_tear_check *cfg);
/**
* @disable_tearcheck: disables tear check block
*/
int (*disable_tearcheck)(struct dpu_hw_pingpong *pp);
/**
* @connect_external_te: read, modify, write to either set or clear
* listening to external TE
* @Return: 1 if TE was originally connected, 0 if not, or -ERROR
*/
int (*connect_external_te)(struct dpu_hw_pingpong *pp,
bool enable_external_te);
/**
* @get_line_count: Obtain current vertical line counter
*/
u32 (*get_line_count)(struct dpu_hw_pingpong *pp);
/**
* @disable_autorefresh: Disable autorefresh if enabled
*/
void (*disable_autorefresh)(struct dpu_hw_pingpong *pp, uint32_t encoder_id, u16 vdisplay);
/**
* @setup_dither: Setup dither matix for pingpong block
*/
void (*setup_dither)(struct dpu_hw_pingpong *pp,
struct dpu_hw_dither_cfg *cfg);
/**
* @enable_dsc: Enable DSC
*/
int (*enable_dsc)(struct dpu_hw_pingpong *pp);
/**
* @disable_dsc: Disable DSC
*/
void (*disable_dsc)(struct dpu_hw_pingpong *pp);
/**
* @setup_dsc: Setup DSC
*/
int (*setup_dsc)(struct dpu_hw_pingpong *pp);
};
struct dpu_hw_merge_3d;
struct dpu_hw_pingpong {
struct dpu_hw_blk base;
struct dpu_hw_blk_reg_map hw;
/* pingpong */
enum dpu_pingpong idx;
const struct dpu_pingpong_cfg *caps;
struct dpu_hw_merge_3d *merge_3d;
/* ops */
struct dpu_hw_pingpong_ops ops;
};
/**
* to_dpu_hw_pingpong - convert base object dpu_hw_base to container
* @hw: Pointer to base hardware block
* return: Pointer to hardware block container
*/
Annotation
- Immediate include surface: `dpu_hw_catalog.h`, `dpu_hw_mdss.h`, `dpu_hw_util.h`.
- Detected declarations: `struct dpu_hw_pingpong`, `struct dpu_hw_dither_cfg`, `struct dpu_hw_pingpong_ops`, `struct dpu_hw_merge_3d`, `struct dpu_hw_pingpong`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.