drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c- Extension
.c- Size
- 22891 bytes
- Lines
- 758
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/debugfs.hdpu_hwio.hdpu_hw_catalog.hdpu_hw_lm.hdpu_hw_sspp.hdpu_kms.hdrm/drm_file.hdrm/drm_managed.hlinux/soc/qcom/ubwc.h
Detected Declarations
function dpu_hw_sspp_setup_multirectfunction dpu_hw_setup_multirect_implfunction dpu_hw_sspp_setup_opmodefunction dpu_hw_sspp_setup_csc10_opmodefunction dpu_hw_sspp_setup_formatfunction dpu_hw_setup_format_implfunction dpu_hw_sspp_setup_pe_configfunction dpu_hw_sspp_setup_scaler3function dpu_hw_sspp_setup_rectsfunction dpu_hw_sspp_setup_sourceaddressfunction dpu_hw_sspp_setup_cscfunction dpu_hw_sspp_setup_solidfillfunction dpu_hw_setup_solidfill_implfunction dpu_hw_sspp_setup_qos_lutfunction dpu_hw_sspp_setup_qos_ctrl_implfunction dpu_hw_sspp_setup_qos_ctrlfunction dpu_hw_sspp_setup_cdpfunction dpu_hw_sspp_setup_clk_force_ctrlfunction _setup_layer_opsfunction _dpu_hw_sspp_init_debugfsfunction dpu_hw_sspp_init
Annotated Snippet
if (ctx->mdss_ver->core_major_ver >= 8) {
ubwc_ctrl_off = SSPP_UBWC_STATIC_CTRL_REC1;
ubwc_error_off = SSPP_UBWC_ERROR_STATUS_REC1;
} else {
ubwc_ctrl_off = SSPP_UBWC_STATIC_CTRL;
ubwc_error_off = SSPP_UBWC_ERROR_STATUS;
}
}
if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
u32 hbb = ctx->ubwc->highest_bank_bit - 13;
DPU_REG_WRITE(&ctx->hw, SSPP_FETCH_CONFIG,
DPU_FETCH_CONFIG_RESET_VALUE |
hbb << 18);
}
dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
unpack_pat_off, format_off,
ubwc_ctrl_off, ubwc_error_off);
}
void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off,
u32 unpack_pat_off, u32 format_off, u32 ubwc_ctrl_off,
u32 ubwc_error_off)
{
struct dpu_hw_blk_reg_map *c;
u32 chroma_samp, unpack, src_format;
u32 opmode;
u32 fast_clear;
c = &ctx->hw;
opmode = DPU_REG_READ(c, op_mode_off);
opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE);
if (flags & DPU_SSPP_FLIP_LR)
opmode |= MDSS_MDP_OP_FLIP_LR;
if (flags & DPU_SSPP_FLIP_UD)
opmode |= MDSS_MDP_OP_FLIP_UD;
chroma_samp = fmt->chroma_sample;
if (flags & DPU_SSPP_SOURCE_ROTATED_90) {
if (chroma_samp == CHROMA_H2V1)
chroma_samp = CHROMA_H1V2;
else if (chroma_samp == CHROMA_H1V2)
chroma_samp = CHROMA_H2V1;
}
src_format = (chroma_samp << 23) | (fmt->fetch_type << 19) |
(fmt->bpc_a << 6) | (fmt->bpc_r_cr << 4) |
(fmt->bpc_b_cb << 2) | (fmt->bpc_g_y << 0);
if (flags & DPU_SSPP_ROT_90)
src_format |= BIT(11); /* ROT90 */
if (fmt->alpha_enable && fmt->fetch_type == MDP_PLANE_INTERLEAVED)
src_format |= BIT(8); /* SRCC3_EN */
if (flags & DPU_SSPP_SOLID_FILL)
src_format |= BIT(22);
unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) |
(fmt->element[1] << 8) | (fmt->element[0] << 0);
src_format |= ((fmt->unpack_count - 1) << 12) |
((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
((fmt->flags & MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB ? 1 : 0) << 18) |
((fmt->bpp - 1) << 9);
if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
u32 hbb = ctx->ubwc->highest_bank_bit - 13;
u32 ctrl_val = 0;
if (MSM_FORMAT_IS_UBWC(fmt))
opmode |= MDSS_MDP_OP_BWC_EN;
src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
if (ctx->ubwc->ubwc_enc_version > UBWC_6_0) {
DRM_WARN_ONCE("Unsupported UBWC version %x\n", ctx->ubwc->ubwc_enc_version);
} else if (ctx->ubwc->ubwc_enc_version >= UBWC_5_0) {
if (!MSM_FORMAT_IS_YUV(fmt)) {
ctrl_val = BIT(30);
if (!MSM_FORMAT_IS_DX(fmt)) /* and not FP16, but it's unsupported */
ctrl_val |= BIT(31);
}
/* SDE also sets bits for lossy formats, but we don't support them yet */
} else if (ctx->ubwc->ubwc_enc_version >= UBWC_4_0) {
ctrl_val = MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30);
} else if (ctx->ubwc->ubwc_enc_version >= UBWC_3_0) {
Annotation
- Immediate include surface: `linux/debugfs.h`, `dpu_hwio.h`, `dpu_hw_catalog.h`, `dpu_hw_lm.h`, `dpu_hw_sspp.h`, `dpu_kms.h`, `drm/drm_file.h`, `drm/drm_managed.h`.
- Detected declarations: `function dpu_hw_sspp_setup_multirect`, `function dpu_hw_setup_multirect_impl`, `function dpu_hw_sspp_setup_opmode`, `function dpu_hw_sspp_setup_csc10_opmode`, `function dpu_hw_sspp_setup_format`, `function dpu_hw_setup_format_impl`, `function dpu_hw_sspp_setup_pe_config`, `function dpu_hw_sspp_setup_scaler3`, `function dpu_hw_sspp_setup_rects`, `function dpu_hw_sspp_setup_sourceaddress`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.