drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
Extension: .c
Size: 12146 bytes
Lines: 324
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/printk.h
linux/soc/qcom/ubwc.h
dpu_hw_sspp.h

Detected Declarations

function Copyright
function dpu_hw_sspp_setup_multirect_v13
function dpu_hw_sspp_setup_format_v13
function dpu_hw_sspp_setup_pe_config_v13
function dpu_hw_sspp_setup_rects_v13
function dpu_hw_sspp_setup_sourceaddress_v13
function dpu_hw_sspp_setup_solidfill_v13
function dpu_hw_sspp_setup_qos_lut_v13
function dpu_hw_sspp_setup_qos_ctrl_v13
function dpu_hw_sspp_setup_cdp_v13
function dpu_hw_sspp_setup_clk_force_ctrl_v13
function dpu_hw_sspp_init_v13

Annotated Snippet

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
 */

#include <linux/printk.h>
#include <linux/soc/qcom/ubwc.h>

#include "dpu_hw_sspp.h"

/* >= v13 DPU */
/* CMN Registers -> Source Surface Processing Pipe Common SSPP registers */
/*      Name                                  Offset */
#define SSPP_CMN_CLK_CTRL                0x0
#define SSPP_CMN_CLK_STATUS              0x4
#define SSPP_CMN_MULTI_REC_OP_MODE       0x10
#define SSPP_CMN_ADDR_CONFIG             0x14
#define SSPP_CMN_CAC_CTRL                0x20
#define SSPP_CMN_SYS_CACHE_MODE          0x24
#define SSPP_CMN_QOS_CTRL                0x28

#define SSPP_CMN_FILL_LEVEL_SCALE                0x3c
#define SSPP_CMN_FILL_LEVELS                     0x40
#define SSPP_CMN_STATUS                          0x44
#define SSPP_CMN_FETCH_DMA_RD_OTS                0x48
#define SSPP_CMN_FETCH_DTB_WR_PLANE0             0x4c
#define SSPP_CMN_FETCH_DTB_WR_PLANE1             0x50
#define SSPP_CMN_FETCH_DTB_WR_PLANE2             0x54
#define SSPP_CMN_DTB_UNPACK_RD_PLANE0            0x58
#define SSPP_CMN_DTB_UNPACK_RD_PLANE1            0x5c
#define SSPP_CMN_DTB_UNPACK_RD_PLANE2            0x60
#define SSPP_CMN_UNPACK_LINE_COUNT               0x64
#define SSPP_CMN_TPG_CONTROL                     0x68
#define SSPP_CMN_TPG_CONFIG                      0x6c
#define SSPP_CMN_TPG_COMPONENT_LIMITS            0x70
#define SSPP_CMN_TPG_RECTANGLE                   0x74
#define SSPP_CMN_TPG_BLACK_WHITE_PATTERN_FRAMES  0x78
#define SSPP_CMN_TPG_RGB_MAPPING                 0x7c
#define SSPP_CMN_TPG_PATTERN_GEN_INIT_VAL        0x80

/*RECRegisterset*/
/*Name        Offset*/
#define SSPP_REC_SRC_FORMAT                             0x0
#define SSPP_REC_SRC_UNPACK_PATTERN                     0x4
#define SSPP_REC_SRC_OP_MODE                            0x8
#define SSPP_REC_SRC_CONSTANT_COLOR                     0xc
#define SSPP_REC_SRC_IMG_SIZE                           0x10
#define SSPP_REC_SRC_SIZE                               0x14
#define SSPP_REC_SRC_XY                                 0x18
#define SSPP_REC_OUT_SIZE                               0x1c
#define SSPP_REC_OUT_XY                                 0x20
#define SSPP_REC_SW_PIX_EXT_LR                          0x24
#define SSPP_REC_SW_PIX_EXT_TB                          0x28
#define SSPP_REC_SRC_SIZE_ODX                           0x30
#define SSPP_REC_SRC_XY_ODX                             0x34
#define SSPP_REC_OUT_SIZE_ODX                           0x38
#define SSPP_REC_OUT_XY_ODX                             0x3c
#define SSPP_REC_SW_PIX_EXT_LR_ODX                      0x40
#define SSPP_REC_SW_PIX_EXT_TB_ODX                      0x44
#define SSPP_REC_PRE_DOWN_SCALE                         0x48
#define SSPP_REC_SRC0_ADDR                              0x4c
#define SSPP_REC_SRC1_ADDR                              0x50
#define SSPP_REC_SRC2_ADDR                              0x54
#define SSPP_REC_SRC3_ADDR                              0x58
#define SSPP_REC_SRC_YSTRIDE0                           0x5c
#define SSPP_REC_SRC_YSTRIDE1                           0x60
#define SSPP_REC_CURRENT_SRC0_ADDR                      0x64
#define SSPP_REC_CURRENT_SRC1_ADDR                      0x68
#define SSPP_REC_CURRENT_SRC2_ADDR                      0x6c
#define SSPP_REC_CURRENT_SRC3_ADDR                      0x70
#define SSPP_REC_SRC_ADDR_SW_STATUS                     0x74
#define SSPP_REC_CDP_CNTL                               0x78
#define SSPP_REC_TRAFFIC_SHAPER                         0x7c
#define SSPP_REC_TRAFFIC_SHAPER_PREFILL                 0x80
#define SSPP_REC_PD_MEM_ALLOC                           0x84
#define SSPP_REC_QOS_CLAMP                              0x88
#define SSPP_REC_UIDLE_CTRL_VALUE                       0x8c
#define SSPP_REC_UBWC_STATIC_CTRL                       0x90
#define SSPP_REC_UBWC_STATIC_CTRL_OVERRIDE              0x94
#define SSPP_REC_UBWC_STATS_ROI                         0x98
#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI0      0x9c
#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI0               0xa0
#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI1      0xa4
#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI1               0xa8
#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI2      0xac
#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI2               0xb0
#define SSPP_REC_EXCL_REC_CTRL                          0xb4
#define SSPP_REC_EXCL_REC_SIZE                          0xb8
#define SSPP_REC_EXCL_REC_XY                            0xbc
#define SSPP_REC_LINE_INSERTION_CTRL                    0xc0

Annotation

Immediate include surface: `linux/printk.h`, `linux/soc/qcom/ubwc.h`, `dpu_hw_sspp.h`.
Detected declarations: `function Copyright`, `function dpu_hw_sspp_setup_multirect_v13`, `function dpu_hw_sspp_setup_format_v13`, `function dpu_hw_sspp_setup_pe_config_v13`, `function dpu_hw_sspp_setup_rects_v13`, `function dpu_hw_sspp_setup_sourceaddress_v13`, `function dpu_hw_sspp_setup_solidfill_v13`, `function dpu_hw_sspp_setup_qos_lut_v13`, `function dpu_hw_sspp_setup_qos_ctrl_v13`, `function dpu_hw_sspp_setup_cdp_v13`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.