drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
Extension
.h
Size
4381 bytes
Lines
165
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct traffic_shaper_cfg {
	bool en;
	bool rd_client;
	u32 client_id;
	u32 bpc_denom;
	u64 bpc_numer;
};

/**
 * struct split_pipe_cfg - pipe configuration for dual display panels
 * @en        : Enable/disable dual pipe configuration
 * @mode      : Panel interface mode
 * @intf      : Interface id for main control path
 * @split_flush_en: Allows both the paths to be flushed when master path is
 *              flushed
 */
struct split_pipe_cfg {
	bool en;
	enum dpu_intf_mode mode;
	enum dpu_intf intf;
	bool split_flush_en;
};

/**
 * struct dpu_danger_safe_status: danger and safe status signals
 * @mdp: top level status
 * @sspp: source pipe status
 */
struct dpu_danger_safe_status {
	u8 mdp;
	u8 sspp[SSPP_MAX];
};

/**
 * struct dpu_vsync_source_cfg - configure vsync source and configure the
 *                                    watchdog timers if required.
 * @pp_count: number of ping pongs active
 * @frame_rate: Display frame rate
 * @ppnumber: ping pong index array
 * @vsync_source: vsync source selection
 */
struct dpu_vsync_source_cfg {
	u32 pp_count;
	u32 frame_rate;
	u32 ppnumber[PINGPONG_MAX];
	enum dpu_vsync_source vsync_source;
};

enum dpu_dp_phy_sel {
	DPU_DP_PHY_NONE,
	DPU_DP_PHY_0,
	DPU_DP_PHY_1,
	DPU_DP_PHY_2,
};

/**
 * struct dpu_hw_mdp_ops - interface to the MDP TOP Hw driver functions
 * Assumption is these functions will be called after clocks are enabled.
 */
struct dpu_hw_mdp_ops {
	/**
	 * @setup_split_pipe : Programs the pipe control registers.
	 * Registers are not double buffered, this
	 * function should be called before timing control enable
	 * @mdp  : mdp top context driver
	 * @cfg  : upper and lower part of pipe configuration
	 */
	void (*setup_split_pipe)(struct dpu_hw_mdp *mdp,
			struct split_pipe_cfg *p);

	/**
	 * @setup_traffic_shaper : programs traffic shaper control.
	 * @mdp  : mdp top context driver
	 * @cfg  : traffic shaper configuration
	 */
	void (*setup_traffic_shaper)(struct dpu_hw_mdp *mdp,
			struct traffic_shaper_cfg *cfg);

	/**
	 * @setup_clk_force_ctrl: set clock force control
	 * @mdp: mdp top context driver
	 * @clk_ctrl: clock to be controlled
	 * @enable: force on enable
	 * @return: if the clock is forced-on by this function
	 */
	bool (*setup_clk_force_ctrl)(struct dpu_hw_mdp *mdp,
			enum dpu_clk_ctrl_type clk_ctrl, bool enable);

	/**
	 * @get_danger_status: get danger status

Annotation

Implementation Notes