drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
Extension
.h
Size
3893 bytes
Lines
130
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dpu_rm {
	struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
	struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
	struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
	struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0];
	struct dpu_hw_wb *hw_wb[WB_MAX - WB_0];
	struct dpu_hw_blk *cwb_blks[CWB_MAX - CWB_0];
	struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
	struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
	struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
	struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
	struct dpu_hw_blk *cdm_blk;
	bool has_legacy_ctls;
};

struct dpu_rm_sspp_requirements {
	bool yuv;
	bool scale;
	bool rot90;
};

/**
 * struct msm_display_topology - defines a display topology pipeline
 * @num_lm:       number of layer mixers used
 * @num_intf:     number of interfaces the panel is mounted on
 * @num_dspp:     number of dspp blocks used
 * @num_dsc:      number of Display Stream Compression (DSC) blocks used
 * @num_cdm:      indicates how many outputs are requesting cdm block for
 *                    this display topology
 * @cwb_enabled:  indicates whether CWB is enabled for this display topology
 */
struct msm_display_topology {
	u32 num_lm;
	u32 num_intf;
	u32 num_dspp;
	u32 num_dsc;
	int num_cdm;
	bool cwb_enabled;
};

int dpu_rm_init(struct drm_device *dev,
		struct dpu_rm *rm,
		const struct dpu_mdss_cfg *cat,
		const struct qcom_ubwc_cfg_data *mdss_data,
		void __iomem *mmio);

int dpu_rm_reserve(struct dpu_rm *rm,
		struct dpu_global_state *global_state,
		struct drm_crtc *crtc,
		struct msm_display_topology *topology);

void dpu_rm_release(struct dpu_global_state *global_state,
		struct drm_crtc *crtc);

struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *rm,
					struct dpu_global_state *global_state,
					struct drm_crtc *crtc,
					struct dpu_rm_sspp_requirements *reqs);

void dpu_rm_release_all_sspp(struct dpu_global_state *global_state,
			     struct drm_crtc *crtc);

int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
	struct dpu_global_state *global_state, struct drm_crtc *crtc,
	enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);

void dpu_rm_print_state(struct drm_printer *p,
			const struct dpu_global_state *global_state);

/**
 * dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index.
 * @rm: DPU Resource Manager handle
 * @intf_idx: INTF's index
 */
static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx)
{
	return rm->hw_intf[intf_idx - INTF_0];
}

/**
 * dpu_rm_get_wb - Return a struct dpu_hw_wb instance given it's index.
 * @rm: DPU Resource Manager handle
 * @wb_idx: WB index
 */
static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_idx)
{
	return rm->hw_wb[wb_idx - WB_0];
}

/**

Annotation

Implementation Notes