drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h- Extension
.h- Size
- 3112 bytes
- Lines
- 137
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
msm_drv.h
Detected Declarations
struct mdp5_sub_blockstruct mdp5_lm_instancestruct mdp5_lm_blockstruct mdp5_pipe_blockstruct mdp5_ctl_blockstruct mdp5_smp_blockstruct mdp5_mdp_blockstruct mdp5_wb_instancestruct mdp5_wb_blockstruct mdp5_intf_blockstruct mdp5_perf_blockstruct mdp5_cfg_hwstruct mdp5_cfgstruct mdp5_kmsstruct mdp5_cfg_handler
Annotated Snippet
struct mdp5_sub_block {
MDP5_SUB_BLOCK_DEFINITION;
};
struct mdp5_lm_instance {
int id;
int pp;
int dspp;
uint32_t caps;
};
struct mdp5_lm_block {
MDP5_SUB_BLOCK_DEFINITION;
struct mdp5_lm_instance instances[MAX_BASES];
uint32_t nb_stages; /* number of stages per blender */
uint32_t max_width; /* Maximum output resolution */
uint32_t max_height;
};
struct mdp5_pipe_block {
MDP5_SUB_BLOCK_DEFINITION;
uint32_t caps; /* pipe capabilities */
};
struct mdp5_ctl_block {
MDP5_SUB_BLOCK_DEFINITION;
uint32_t flush_hw_mask; /* FLUSH register's hardware mask */
};
struct mdp5_smp_block {
int mmb_count; /* number of SMP MMBs */
int mmb_size; /* MMB: size in bytes */
uint32_t clients[MAX_CLIENTS]; /* SMP port allocation /pipe */
mdp5_smp_state_t reserved_state;/* SMP MMBs statically allocated */
uint8_t reserved[MAX_CLIENTS]; /* # of MMBs allocated per client */
};
struct mdp5_mdp_block {
MDP5_SUB_BLOCK_DEFINITION;
uint32_t caps; /* MDP capabilities: MDP_CAP_xxx bits */
};
struct mdp5_wb_instance {
int id;
int lm;
};
struct mdp5_wb_block {
MDP5_SUB_BLOCK_DEFINITION;
struct mdp5_wb_instance instances[MAX_BASES];
};
#define MDP5_INTF_NUM_MAX 5
struct mdp5_intf_block {
uint32_t base[MAX_BASES];
u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
};
struct mdp5_perf_block {
u32 ab_inefficiency;
u32 ib_inefficiency;
u32 clk_inefficiency;
};
struct mdp5_cfg_hw {
char *name;
struct mdp5_mdp_block mdp;
struct mdp5_smp_block smp;
struct mdp5_ctl_block ctl;
struct mdp5_pipe_block pipe_vig;
struct mdp5_pipe_block pipe_rgb;
struct mdp5_pipe_block pipe_dma;
struct mdp5_pipe_block pipe_cursor;
struct mdp5_lm_block lm;
struct mdp5_sub_block dspp;
struct mdp5_sub_block ad;
struct mdp5_sub_block pp;
struct mdp5_sub_block dsc;
struct mdp5_sub_block cdm;
struct mdp5_wb_block wb;
struct mdp5_intf_block intf;
struct mdp5_perf_block perf;
uint32_t max_clk;
};
struct mdp5_cfg {
const struct mdp5_cfg_hw *hw;
Annotation
- Immediate include surface: `msm_drv.h`.
- Detected declarations: `struct mdp5_sub_block`, `struct mdp5_lm_instance`, `struct mdp5_lm_block`, `struct mdp5_pipe_block`, `struct mdp5_ctl_block`, `struct mdp5_smp_block`, `struct mdp5_mdp_block`, `struct mdp5_wb_instance`, `struct mdp5_wb_block`, `struct mdp5_intf_block`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.