drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h- Extension
.h- Size
- 8495 bytes
- Lines
- 318
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
msm_drv.hmsm_kms.hdisp/mdp_kms.hmdp5_cfg.hmdp5.xml.hmdp5_pipe.hmdp5_mixer.hmdp5_ctl.hmdp5_smp.h
Detected Declarations
struct mdp5_kmsstruct mdp5_global_statestruct mdp5_plane_statestruct mdp5_pipelinestruct mdp5_crtc_statestruct mdp5_interfacestruct mdp5_encoderenum mdp5_intf_modefunction mdp5_writefunction mdp5_readfunction pipe2nclientsfunction intf2errfunction intf2vblankfunction lm2ppdonefunction mdp5_cmd_encoder_mode_set
Annotated Snippet
struct mdp5_kms {
struct mdp_kms base;
struct drm_device *dev;
struct platform_device *pdev;
unsigned num_hwpipes;
struct mdp5_hw_pipe *hwpipes[SSPP_MAX];
unsigned num_hwmixers;
struct mdp5_hw_mixer *hwmixers[8];
unsigned num_intfs;
struct mdp5_interface *intfs[5];
struct mdp5_cfg_handler *cfg;
uint32_t caps; /* MDP capabilities (MDP_CAP_XXX bits) */
/*
* Global private object state, Do not access directly, use
* mdp5_global_get_state()
*/
struct drm_private_obj glob_state;
struct mdp5_smp *smp;
struct mdp5_ctl_manager *ctlm;
/* io/register spaces: */
void __iomem *mmio;
struct clk *axi_clk;
struct clk *ahb_clk;
struct clk *core_clk;
struct clk *lut_clk;
struct clk *tbu_clk;
struct clk *tbu_rt_clk;
struct clk *vsync_clk;
/*
* lock to protect access to global resources: ie., following register:
* - REG_MDP5_DISP_INTF_SEL
*/
spinlock_t resource_lock;
bool rpm_enabled;
struct mdp_irq error_handler;
int enable_count;
};
#define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
/* Global private object state for tracking resources that are shared across
* multiple kms objects (planes/crtcs/etc).
*/
#define to_mdp5_global_state(x) container_of(x, struct mdp5_global_state, base)
struct mdp5_global_state {
struct drm_private_state base;
struct drm_atomic_commit *state;
struct mdp5_kms *mdp5_kms;
struct mdp5_hw_pipe_state hwpipe;
struct mdp5_hw_mixer_state hwmixer;
struct mdp5_smp_state smp;
};
struct mdp5_global_state * mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms);
struct mdp5_global_state *__must_check mdp5_get_global_state(struct drm_atomic_commit *s);
/* Atomic plane state. Subclasses the base drm_plane_state in order to
* track assigned hwpipe and hw specific state.
*/
struct mdp5_plane_state {
struct drm_plane_state base;
struct mdp5_hw_pipe *hwpipe;
struct mdp5_hw_pipe *r_hwpipe; /* right hwpipe */
/* assigned by crtc blender */
enum mdp_mixer_stage_id stage;
/* whether attached CRTC needs pixel data explicitly flushed to
* display (ex. DSI command mode display)
*/
bool needs_dirtyfb;
};
#define to_mdp5_plane_state(x) \
container_of(x, struct mdp5_plane_state, base)
Annotation
- Immediate include surface: `msm_drv.h`, `msm_kms.h`, `disp/mdp_kms.h`, `mdp5_cfg.h`, `mdp5.xml.h`, `mdp5_pipe.h`, `mdp5_mixer.h`, `mdp5_ctl.h`.
- Detected declarations: `struct mdp5_kms`, `struct mdp5_global_state`, `struct mdp5_plane_state`, `struct mdp5_pipeline`, `struct mdp5_crtc_state`, `struct mdp5_interface`, `struct mdp5_encoder`, `enum mdp5_intf_mode`, `function mdp5_write`, `function mdp5_read`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.