drivers/gpu/drm/msm/dp/dp_reg.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/dp/dp_reg.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/dp/dp_reg.h
Extension
.h
Size
14313 bytes
Lines
367
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DP_REG_H_
#define _DP_REG_H_

#include <linux/bitfield.h>
#include <linux/bits.h>

/* DP_TX Registers */
#define REG_DP_HW_VERSION			(0x00000000)
#define DP_HW_VERSION_1_0	0x10000000
#define DP_HW_VERSION_1_2	0x10020000

#define REG_DP_SW_RESET				(0x00000010)
#define DP_SW_RESET				(0x00000001)

#define REG_DP_PHY_CTRL				(0x00000014)
#define DP_PHY_CTRL_SW_RESET_PLL		(0x00000001)
#define DP_PHY_CTRL_SW_RESET			(0x00000004)

#define REG_DP_CLK_CTRL				(0x00000018)
#define REG_DP_CLK_ACTIVE			(0x0000001C)

#define REG_DP_INTR_STATUS			(0x00000020)
#define DP_INTR_HPD		BIT(0)
#define DP_INTR_AUX_XFER_DONE	BIT(3)
#define DP_INTR_WRONG_ADDR	BIT(6)
#define DP_INTR_TIMEOUT		BIT(9)
#define DP_INTR_NACK_DEFER	BIT(12)
#define DP_INTR_WRONG_DATA_CNT	BIT(15)
#define DP_INTR_I2C_NACK	BIT(18)
#define DP_INTR_I2C_DEFER	BIT(21)
#define DP_INTR_PLL_UNLOCKED	BIT(24)
#define DP_INTR_AUX_ERROR	BIT(27)

#define REG_DP_INTR_STATUS2			(0x00000024)
#define DP_INTR_READY_FOR_VIDEO		BIT(0)
#define DP_INTR_IDLE_PATTERN_SENT	BIT(3)
#define DP_INTR_FRAME_END		BIT(6)
#define DP_INTR_CRC_UPDATED		BIT(9)

#define REG_DP_INTR_STATUS3			(0x00000028)

#define REG_DP_INTR_STATUS4			(0x0000002C)
#define PSR_UPDATE_INT				(0x00000001)
#define PSR_CAPTURE_INT				(0x00000004)
#define PSR_EXIT_INT				(0x00000010)
#define PSR_UPDATE_ERROR_INT			(0x00000040)
#define PSR_WAKE_ERROR_INT			(0x00000100)

#define REG_DP_INTR_MASK4			(0x00000030)
#define PSR_UPDATE_MASK				(0x00000001)
#define PSR_CAPTURE_MASK			(0x00000002)
#define PSR_EXIT_MASK				(0x00000004)
#define PSR_UPDATE_ERROR_MASK			(0x00000008)
#define PSR_WAKE_ERROR_MASK			(0x00000010)

#define REG_DP_DP_HPD_CTRL			(0x00000000)
#define DP_DP_HPD_CTRL_HPD_EN			(0x00000001)

#define REG_DP_DP_HPD_INT_STATUS		(0x00000004)

#define REG_DP_DP_HPD_INT_ACK			(0x00000008)
#define DP_DP_HPD_PLUG_INT_ACK			(0x00000001)
#define DP_DP_IRQ_HPD_INT_ACK			(0x00000002)
#define DP_DP_HPD_REPLUG_INT_ACK		(0x00000004)
#define DP_DP_HPD_UNPLUG_INT_ACK		(0x00000008)
#define DP_DP_HPD_STATE_STATUS_BITS_MASK	(0x00000007)
#define DP_DP_HPD_STATE_STATUS_BITS_SHIFT	(0x1D)

#define REG_DP_DP_HPD_INT_MASK			(0x0000000C)
#define DP_DP_HPD_PLUG_INT_MASK			(0x00000001)
#define DP_DP_IRQ_HPD_INT_MASK			(0x00000002)
#define DP_DP_HPD_REPLUG_INT_MASK		(0x00000004)
#define DP_DP_HPD_UNPLUG_INT_MASK		(0x00000008)
#define DP_DP_HPD_INT_MASK			(DP_DP_HPD_PLUG_INT_MASK | \
						DP_DP_IRQ_HPD_INT_MASK | \
						DP_DP_HPD_REPLUG_INT_MASK | \
						DP_DP_HPD_UNPLUG_INT_MASK)
#define DP_DP_HPD_STATE_STATUS_CONNECTED	(0x40000000)
#define DP_DP_HPD_STATE_STATUS_PENDING		(0x20000000)
#define DP_DP_HPD_STATE_STATUS_DISCONNECTED	(0x00000000)
#define DP_DP_HPD_STATE_STATUS_MASK		(0xE0000000)

#define REG_DP_DP_HPD_REFTIMER			(0x00000018)
#define DP_DP_HPD_REFTIMER_ENABLE		(1 << 16)

#define REG_DP_DP_HPD_EVENT_TIME_0		(0x0000001C)
#define REG_DP_DP_HPD_EVENT_TIME_1		(0x00000020)
#define DP_DP_HPD_EVENT_TIME_0_VAL		(0x3E800FA)
#define DP_DP_HPD_EVENT_TIME_1_VAL		(0x1F407D0)

Annotation

Implementation Notes