drivers/gpu/drm/msm/msm_gpu.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/msm_gpu.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/msm/msm_gpu.h- Extension
.h- Size
- 22871 bytes
- Lines
- 808
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/adreno-smmu-priv.hlinux/clk.hlinux/devfreq.hlinux/interconnect.hlinux/pm_opp.hlinux/regulator/consumer.hmsm_drv.hmsm_fence.hmsm_gpu_trace.hmsm_ringbuffer.hmsm_gem.h
Detected Declarations
struct msm_gem_submitstruct msm_gem_vm_log_entrystruct msm_gpu_statestruct msm_contextstruct msm_perfcntr_groupstruct msm_perfcntr_streamstruct msm_gpu_configstruct msm_gpu_funcsstruct msm_gpu_fault_infostruct msm_gpu_devfreqstruct msm_gpustruct msm_perfcntr_group_statestruct msm_perfcntr_statestruct msm_contextstruct msm_gpu_submitqueuestruct msm_gpu_state_bostruct msm_gpu_statefunction adreno_smmu_has_prrfunction AXXX_CP_RB_CNTL_BLKSZfunction msm_gpu_sysprof_no_perfcntr_zapfunction msm_gpu_sysprof_no_ifpcfunction msm_context_is_vmbindfunction isfunction gpu_writefunction gpu_readfunction gpu_rmwfunction gpu_read64function gpu_write64function msm_context_putfunction msm_submitqueue_putfunction msm_gpu_crashstate_put
Annotated Snippet
struct msm_gpu_config {
const char *ioname;
unsigned int nr_rings;
};
/* So far, with hardware that I've seen to date, we can have:
* + zero, one, or two z180 2d cores
* + a3xx or a2xx 3d core, which share a common CP (the firmware
* for the CP seems to implement some different PM4 packet types
* but the basics of cmdstream submission are the same)
*
* Which means that the eventual complete "class" hierarchy, once
* support for all past and present hw is in place, becomes:
* + msm_gpu
* + adreno_gpu
* + a3xx_gpu
* + a2xx_gpu
* + z180_gpu
*/
struct msm_gpu_funcs {
int (*get_param)(struct msm_gpu *gpu, struct msm_context *ctx,
uint32_t param, uint64_t *value, uint32_t *len);
int (*set_param)(struct msm_gpu *gpu, struct msm_context *ctx,
uint32_t param, uint64_t value, uint32_t len);
int (*hw_init)(struct msm_gpu *gpu);
/**
* @ucode_load: Optional hook to upload fw to GEM objs
*/
int (*ucode_load)(struct msm_gpu *gpu);
int (*pm_suspend)(struct msm_gpu *gpu);
int (*pm_resume)(struct msm_gpu *gpu);
void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
irqreturn_t (*irq)(struct msm_gpu *irq);
struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
void (*recover)(struct msm_gpu *gpu);
void (*destroy)(struct msm_gpu *gpu);
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
/* show GPU status in debugfs: */
void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
struct drm_printer *p);
/* for generation specific debugfs: */
void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
#endif
/* note: gpu_busy() can assume that we have been pm_resumed */
u64 (*gpu_busy)(struct msm_gpu *gpu, unsigned long *out_sample_rate);
struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
int (*gpu_state_put)(struct msm_gpu_state *state);
unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
/* note: gpu_set_freq() can assume that we have been pm_resumed */
void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp,
bool suspended);
struct drm_gpuvm *(*create_vm)(struct msm_gpu *gpu, struct platform_device *pdev);
struct drm_gpuvm *(*create_private_vm)(struct msm_gpu *gpu, bool kernel_managed);
uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
/**
* progress: Has the GPU made progress?
*
* Return true if GPU position in cmdstream has advanced (or changed)
* since the last call. To avoid false negatives, this should account
* for cmdstream that is buffered in this FIFO upstream of the CP fw.
*/
bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
void (*sysprof_setup)(struct msm_gpu *gpu, bool force_on);
/* Configure perfcntr SELect regs: */
void (*perfcntr_configure)(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
const struct msm_perfcntr_stream *stream);
/* Flush perfcntrs before reading (optional): */
void (*perfcntr_flush)(struct msm_gpu *gpu);
};
/* Additional state for iommu faults: */
struct msm_gpu_fault_info {
u64 ttbr0;
unsigned long iova;
int flags;
const char *type;
const char *block;
/* Information about what we think/expect is the current SMMU state,
* for example expected_ttbr0 should match smmu_info.ttbr0 which
* was read back from SMMU registers.
*/
phys_addr_t pgtbl_ttbr0;
u64 ptes[4];
Annotation
- Immediate include surface: `linux/adreno-smmu-priv.h`, `linux/clk.h`, `linux/devfreq.h`, `linux/interconnect.h`, `linux/pm_opp.h`, `linux/regulator/consumer.h`, `msm_drv.h`, `msm_fence.h`.
- Detected declarations: `struct msm_gem_submit`, `struct msm_gem_vm_log_entry`, `struct msm_gpu_state`, `struct msm_context`, `struct msm_perfcntr_group`, `struct msm_perfcntr_stream`, `struct msm_gpu_config`, `struct msm_gpu_funcs`, `struct msm_gpu_fault_info`, `struct msm_gpu_devfreq`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.