drivers/gpu/drm/msm/msm_perfcntr.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/msm_perfcntr.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/msm_perfcntr.h
Extension
.h
Size
4576 bytes
Lines
156
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct msm_perfcntr_counter {
	/* offset of the SELect register to choose what to count: */
	unsigned select_reg;
	/* additional SEL regs to enable slice counters (gen8+) */
	unsigned slice_select_regs[2];
	/* offset of the lo/hi 32b to read current counter value: */
	unsigned counter_reg_lo;
	unsigned counter_reg_hi;
	/* TODO some counters have enable/clear registers */
};

/* Describes an entire counter group: */
struct msm_perfcntr_group {
	const char *name;
	enum adreno_pipe pipe;
	unsigned num_counters;
	const struct msm_perfcntr_counter *counters;
};

/**
 * struct msm_perfcntr_stream - state for a single open stream fd
 */
struct msm_perfcntr_stream {
	/** @gpu: Back-link to the GPU */
	struct msm_gpu *gpu;

	/** @sample_timer: Timer to sample counters */
	struct hrtimer sample_timer;

	/** @poll_wq: Wait queue for waiting for OA data to be available */
	wait_queue_head_t poll_wq;

	/** @sample_period_ns: Sampling period */
	uint64_t sample_period_ns;

	/** @nr_groups: # of counter groups with enabled counters */
	uint32_t nr_groups;

	/** @seqno: counter for collected samples */
	uint32_t seqno;

	/** @sel_fence: Fence for SEL reg programming  */
	uint32_t sel_fence;

	/**
	 * @sel_work: Worker for SEL reg programming
	 *
	 * Initial SEL reg programming (as opposed to restoring the SEL
	 * regs on runpm resume) must run on the same ordered wq as is
	 * used by drm_sched, to serialize it with GEM_SUBMITs written
	 * into the same ringbuffer.
	 */
	struct work_struct sel_work;

	/**
	 * @sample_work: Worker for collecting samples
	 */
	struct kthread_work sample_work;

	/**
	 * @read_lock:
	 *
	 * Fifo access is synchronied on the producer side by virtue
	 * of there being a single timer collecting samples and writing
	 * into the fifo.  It is protected on the consumer side by
	 * @read_lock.
	 */
	struct mutex read_lock;

	/**
	 * @group_idx: array of nr_groups
	 *
	 * Maps the order of groups in PERFCNTR_CONFIG ioctl to group idx,
	 * so that results in the results stream can be ordered to match
	 * the ioctl call that setup the stream
	 */
	uint32_t *group_idx;

	/** @fifo: circular buffer for samples */
	struct circ_buf fifo;

	/** @fifo_size: circular buffer size */
	size_t fifo_size;

	/** @period_size: size of data for single sampling period */
	size_t period_size;
};

uint32_t msm_perfcntr_group_idx(const struct msm_perfcntr_stream *stream, uint32_t n);
uint32_t msm_perfcntr_counter_base(const struct msm_perfcntr_stream *stream, uint32_t group_idx);

Annotation

Implementation Notes