drivers/gpu/drm/msm/msm_syncobj.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/msm_syncobj.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/msm/msm_syncobj.c- Extension
.c- Size
- 4069 bytes
- Lines
- 173
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
drm/drm_drv.hmsm_drv.hmsm_syncobj.h
Detected Declarations
function msm_syncobj_parse_depsfunction msm_syncobj_resetfunction msm_syncobj_parse_post_depsfunction msm_syncobj_process_post_deps
Annotated Snippet
min(syncobj_stride, sizeof(syncobj_desc)))) {
ret = -EFAULT;
break;
}
if (syncobj_desc.point &&
!drm_core_check_feature(dev, DRIVER_SYNCOBJ_TIMELINE)) {
ret = UERR(EOPNOTSUPP, dev, "syncobj timeline unsupported");
break;
}
if (syncobj_desc.flags & ~MSM_SYNCOBJ_FLAGS) {
ret = UERR(EINVAL, dev, "invalid syncobj flags: %x", syncobj_desc.flags);
break;
}
ret = drm_sched_job_add_syncobj_dependency(job, file,
syncobj_desc.handle,
syncobj_desc.point);
if (ret)
break;
if (syncobj_desc.flags & MSM_SYNCOBJ_RESET) {
syncobjs[i] = drm_syncobj_find(file, syncobj_desc.handle);
if (!syncobjs[i]) {
ret = UERR(EINVAL, dev, "invalid syncobj handle: %u", i);
break;
}
}
}
if (ret) {
for (j = 0; j <= i; ++j) {
if (syncobjs[j])
drm_syncobj_put(syncobjs[j]);
}
kfree(syncobjs);
return ERR_PTR(ret);
}
return syncobjs;
}
void
msm_syncobj_reset(struct drm_syncobj **syncobjs, uint32_t nr_syncobjs)
{
uint32_t i;
for (i = 0; syncobjs && i < nr_syncobjs; ++i) {
if (syncobjs[i])
drm_syncobj_replace_fence(syncobjs[i], NULL);
}
}
struct msm_syncobj_post_dep *
msm_syncobj_parse_post_deps(struct drm_device *dev,
struct drm_file *file,
uint64_t syncobjs_addr,
uint32_t nr_syncobjs,
size_t syncobj_stride)
{
struct msm_syncobj_post_dep *post_deps;
struct drm_msm_syncobj syncobj_desc = {0};
int ret = 0;
uint32_t i, j;
post_deps = kzalloc_objs(*post_deps, nr_syncobjs,
GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
if (!post_deps)
return ERR_PTR(-ENOMEM);
for (i = 0; i < nr_syncobjs; ++i) {
uint64_t address = syncobjs_addr + i * syncobj_stride;
if (copy_from_user(&syncobj_desc,
u64_to_user_ptr(address),
min(syncobj_stride, sizeof(syncobj_desc)))) {
ret = -EFAULT;
break;
}
post_deps[i].point = syncobj_desc.point;
if (syncobj_desc.flags) {
ret = UERR(EINVAL, dev, "invalid syncobj flags");
break;
}
if (syncobj_desc.point) {
if (!drm_core_check_feature(dev,
DRIVER_SYNCOBJ_TIMELINE)) {
Annotation
- Immediate include surface: `drm/drm_drv.h`, `msm_drv.h`, `msm_syncobj.h`.
- Detected declarations: `function msm_syncobj_parse_deps`, `function msm_syncobj_reset`, `function msm_syncobj_parse_post_deps`, `function msm_syncobj_process_post_deps`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.