drivers/gpu/drm/msm/registers/adreno/a5xx.xml

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/registers/adreno/a5xx.xml

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/msm/registers/adreno/a5xx.xml
Extension: .xml
Size: 149888 bytes
Lines: 2995
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: drivers/gpu
Status: atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>
<import file="adreno/adreno_common.xml"/>
<import file="adreno/adreno_pm4.xml"/>

<enum name="a5xx_color_fmt">
	<value value="0x02" name="RB5_A8_UNORM"/>
	<value value="0x03" name="RB5_R8_UNORM"/>
	<value value="0x04" name="RB5_R8_SNORM"/>
	<value value="0x05" name="RB5_R8_UINT"/>
	<value value="0x06" name="RB5_R8_SINT"/>
	<value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
	<value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
	<value value="0x0e" name="RB5_R5G6B5_UNORM"/>
	<value value="0x0f" name="RB5_R8G8_UNORM"/>
	<value value="0x10" name="RB5_R8G8_SNORM"/>
	<value value="0x11" name="RB5_R8G8_UINT"/>
	<value value="0x12" name="RB5_R8G8_SINT"/>
	<value value="0x15" name="RB5_R16_UNORM"/>
	<value value="0x16" name="RB5_R16_SNORM"/>
	<value value="0x17" name="RB5_R16_FLOAT"/>
	<value value="0x18" name="RB5_R16_UINT"/>
	<value value="0x19" name="RB5_R16_SINT"/>
	<value value="0x30" name="RB5_R8G8B8A8_UNORM"/>
	<value value="0x31" name="RB5_R8G8B8_UNORM"/>
	<value value="0x32" name="RB5_R8G8B8A8_SNORM"/>
	<value value="0x33" name="RB5_R8G8B8A8_UINT"/>
	<value value="0x34" name="RB5_R8G8B8A8_SINT"/>
	<value value="0x37" name="RB5_R10G10B10A2_UNORM"/>  <!-- GL_RGB10_A2 -->
	<value value="0x3a" name="RB5_R10G10B10A2_UINT"/>   <!-- GL_RGB10_A2UI -->
	<value value="0x42" name="RB5_R11G11B10_FLOAT"/>    <!-- GL_R11F_G11F_B10F -->
	<value value="0x43" name="RB5_R16G16_UNORM"/>
	<value value="0x44" name="RB5_R16G16_SNORM"/>
	<value value="0x45" name="RB5_R16G16_FLOAT"/>
	<value value="0x46" name="RB5_R16G16_UINT"/>
	<value value="0x47" name="RB5_R16G16_SINT"/>
	<value value="0x4a" name="RB5_R32_FLOAT"/>
	<value value="0x4b" name="RB5_R32_UINT"/>
	<value value="0x4c" name="RB5_R32_SINT"/>
	<value value="0x60" name="RB5_R16G16B16A16_UNORM"/>
	<value value="0x61" name="RB5_R16G16B16A16_SNORM"/>
	<value value="0x62" name="RB5_R16G16B16A16_FLOAT"/>
	<value value="0x63" name="RB5_R16G16B16A16_UINT"/>
	<value value="0x64" name="RB5_R16G16B16A16_SINT"/>
	<value value="0x67" name="RB5_R32G32_FLOAT"/>
	<value value="0x68" name="RB5_R32G32_UINT"/>
	<value value="0x69" name="RB5_R32G32_SINT"/>
	<value value="0x82" name="RB5_R32G32B32A32_FLOAT"/>
	<value value="0x83" name="RB5_R32G32B32A32_UINT"/>
	<value value="0x84" name="RB5_R32G32B32A32_SINT"/>

	<value value="0xff" name="RB5_NONE"/>
</enum>

<enum name="a5xx_tile_mode">
	<value name="TILE5_LINEAR" value="0"/>
	<value name="TILE5_2" value="2"/>
	<value name="TILE5_3" value="3"/>
</enum>

<enum name="a5xx_vtx_fmt" prefix="chipset">
	<value value="0x03" name="VFMT5_8_UNORM"/>
	<value value="0x04" name="VFMT5_8_SNORM"/>
	<value value="0x05" name="VFMT5_8_UINT"/>
	<value value="0x06" name="VFMT5_8_SINT"/>

	<value value="0x0f" name="VFMT5_8_8_UNORM"/>

Annotation

Atlas domain: Driver Families / drivers/gpu.
Implementation status: atlas-only.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.