drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
Extension
.xml
Size
14766 bytes
Lines
270
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: drivers/gpu
Status
atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>
<import file="adreno/adreno_common.xml"/>

<domain name="A6XX" width="32" prefix="variant" varset="chip">

	<bitset name="A6XX_GMU_GPU_IDLE_STATUS">
		<bitfield name="BUSY_IGN_AHB" pos="23"/>
		<bitfield name="CX_GX_CPU_BUSY_IGN_AHB" pos="30"/>
	</bitset>

	<bitset name="A6XX_GMU_OOB">
		<bitfield name="BOOT_SLUMBER_SET_MASK" pos="22"/>
		<bitfield name="BOOT_SLUMBER_CHECK_MASK" pos="30"/>
		<bitfield name="BOOT_SLUMBER_CLEAR_MASK" pos="30"/>
		<bitfield name="DCVS_SET_MASK" pos="23"/>
		<bitfield name="DCVS_CHECK_MASK" pos="31"/>
		<bitfield name="DCVS_CLEAR_MASK" pos="31"/>
		<bitfield name="GPU_SET_MASK" pos="18"/>
		<bitfield name="GPU_CHECK_MASK" pos="26"/>
		<bitfield name="GPU_CLEAR_MASK" pos="26"/>
		<bitfield name="PERFCNTR_SET_MASK" pos="17"/>
		<bitfield name="PERFCNTR_CHECK_MASK" pos="25"/>
		<bitfield name="PERFCNTR_CLEAR_MASK" pos="25"/>
	</bitset>

	<bitset name="A6XX_HFI_IRQ">
		<bitfield name="MSGQ_MASK" pos="0" />
		<bitfield name="DSGQ_MASK" pos="1"/>
		<bitfield name="BLOCKED_MSG_MASK" pos="2"/>
		<bitfield name="CM3_FAULT_MASK" pos="23"/>
		<bitfield name="GMU_ERR_MASK" low="16" high="22"/>
		<bitfield name="OOB_MASK" low="24" high="31"/>
	</bitset>

	<bitset name="A6XX_HFI_H2F">
		<bitfield name="IRQ_MASK_BIT" pos="0" />
	</bitset>

	<reg32 offset="0x1a880" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
	<reg32 offset="0x1a881" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
	<reg32 offset="0x1b400" name="GMU_CM3_ITCM_START"/>
	<reg32 offset="0x1c400" name="GMU_CM3_DTCM_START"/>
	<reg32 offset="0x1cbf0" name="GMU_NMI_CONTROL_STATUS"/>
	<reg32 offset="0x1cbf8" name="GMU_BOOT_SLUMBER_OPTION"/>
	<reg32 offset="0x1cbf9" name="GMU_GX_VOTE_IDX"/>
	<reg32 offset="0x1cbfa" name="GMU_MX_VOTE_IDX"/>
	<reg32 offset="0x1cbfc" name="GMU_DCVS_ACK_OPTION"/>
	<reg32 offset="0x1cbfd" name="GMU_DCVS_PERF_SETTING"/>
	<reg32 offset="0x1cbfe" name="GMU_DCVS_BW_SETTING"/>
	<reg32 offset="0x1cbff" name="GMU_DCVS_RETURN"/>
	<reg32 offset="0x1d3f8" name="GMU_CORE_FW_VERSION">
		<bitfield name="MAJOR" low="28" high="31"/>
		<bitfield name="MINOR" low="16" high="27"/>
		<bitfield name="STEP" low="0" high="15"/>
	</reg32>
	<reg32 offset="0x1f400" name="GMU_ICACHE_CONFIG"/>
	<reg32 offset="0x1f401" name="GMU_DCACHE_CONFIG"/>
	<reg32 offset="0x1f40f" name="GMU_SYS_BUS_CONFIG"/>
	<reg32 offset="0x1f50b" name="GMU_MRC_GBIF_QOS_CTRL"/>
	<reg32 offset="0x1f800" name="GMU_CM3_SYSRESET"/>
	<reg32 offset="0x1f801" name="GMU_CM3_BOOT_CONFIG"/>
	<reg32 offset="0x1f81a" name="GMU_CM3_FW_BUSY"/>
	<reg32 offset="0x1f81c" name="GMU_CM3_FW_INIT_RESULT"/>
	<reg32 offset="0x1f82d" name="GMU_CM3_CFG"/>
	<reg32 offset="0x1f840" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/>
	<reg32 offset="0x1fc10" name="GMU_CX_GMU_POWER_COUNTER_ENABLE" variants="A8XX"/>

Annotation

Implementation Notes