drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json

Extension

.json

Size

3369 bytes

Lines

113

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

{
    "chip": "A6XX",
    "groups": [
        {
            "name": "CP",
            "num": 14,
            "reserved": [ 0 ],
            "select": "CP_PERFCTR_CP_SEL",
            "counter": "RBBM_PERFCTR_CP",
            "countable_type": "a6xx_cp_perfcounter_select"
        },
        {
            "name": "CCU",
            "num": 5,
            "select": "RB_PERFCTR_CCU_SEL",
            "counter": "RBBM_PERFCTR_CCU",
            "countable_type": "a6xx_ccu_perfcounter_select"
        },
        {
            "name": "TSE",
            "num": 4,
            "select": "GRAS_PERFCTR_TSE_SEL",
            "counter": "RBBM_PERFCTR_TSE",
            "countable_type": "a6xx_tse_perfcounter_select"
        },
        {
            "name": "RAS",
            "num": 4,
            "select": "GRAS_PERFCTR_RAS_SEL",
            "counter": "RBBM_PERFCTR_RAS",
            "countable_type": "a6xx_ras_perfcounter_select"
        },
        {
            "name": "LRZ",
            "num": 4,
            "select": "GRAS_PERFCTR_LRZ_SEL",
            "counter": "RBBM_PERFCTR_LRZ",
            "countable_type": "a6xx_lrz_perfcounter_select"
        },
        {
            "name": "CMP",
            "num": 4,
            "select": "RB_PERFCTR_CMP_SEL",
            "counter": "RBBM_PERFCTR_CMP",
            "countable_type": "a6xx_cmp_perfcounter_select"
        },
        {
            "name": "HLSQ",
            "num": 6,
            "select": "HLSQ_PERFCTR_HLSQ_SEL",
            "counter": "RBBM_PERFCTR_HLSQ",
            "countable_type": "a6xx_hlsq_perfcounter_select"
        },
        {
            "name": "PC",
            "num": 8,
            "select": "PC_PERFCTR_PC_SEL",
            "counter": "RBBM_PERFCTR_PC",
            "countable_type": "a6xx_pc_perfcounter_select"
        },
        {
            "name": "RB",
            "num": 8,
            "select": "RB_PERFCTR_RB_SEL",
            "counter": "RBBM_PERFCTR_RB",
            "countable_type": "a6xx_rb_perfcounter_select"
        },
        {
            "name": "SP",
            "num": 24,

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.