drivers/gpu/drm/msm/registers/adreno/a6xx.xml

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/registers/adreno/a6xx.xml

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/msm/registers/adreno/a6xx.xml
Extension: .xml
Size: 279250 bytes
Lines: 5110
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: drivers/gpu
Status: atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

function buffer
function direction

Annotated Snippet

if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
					kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
					kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
				} ...
		</doc>
		<bitfield name="SDS_START" low="0" high="8" shr="2"/>
		<!-- total ROQ size: -->
		<bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
	</reg32>
	<reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE" variants="A6XX"/>
	<reg32 offset="0x0841" name="CP_CHICKEN_DBG" variants="A6XX-A7XX"/>
	<reg32 offset="0x08b2" name="CP_CHICKEN_DBG_PIPE" variants="A8XX-"/>
	<reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/>
	<reg32 offset="0x0843" name="CP_DBG_ECO_CNTL" variants="A6XX-A7XX"/>
	<reg32 offset="0x084b" name="CP_DBG_ECO_CNTL" variants="A8XX-"/>

	<bitset name="a6xx_cp_protect_cntl" inline="yes">
		<bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/>
		<bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/>
		<bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/>
	</bitset>

	<reg32 offset="0x084f" name="CP_PROTECT_CNTL" type="a6xx_cp_protect_cntl" variants="A6XX-A7XX"/>
	<bitset name="a8xx_cp_protect_cntl" inline="yes">
		<bitfield name="HALT_SQE_RANGE" low="16" high="31"/>
		<bitfield name="LAST_SPAN_INF_RANGE" pos="3" type="boolean"/>
		<bitfield name="ACCESS_FAULT_ON_VIOL_EN" pos="1" type="boolean"/>
		<bitfield name="ACCESS_PROT_EN" pos="0" type="boolean"/>
	</bitset>

	<reg32 offset="0x084e" name="CP_PROTECT_CNTL_PIPE" type="a8xx_cp_protect_cntl" variants="A8XX-"/>

	<array offset="0x0883" name="CP_SCRATCH" stride="1" length="8" variants="A6XX-A7XX">
		<reg32 offset="0x0" name="REG" type="uint"/>
	</array>
	<array offset="0x0850" name="CP_PROTECT" stride="1" length="32" variants="A6XX-A7XX">
		<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
	</array>
	<array offset="0x0850" name="CP_PROTECT_GLOBAL" stride="1" length="64" variants="A8XX-">
		<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
	</array>
	<array offset="0x08a0" name="CP_PROTECT_PIPE" stride="1" length="16" variants="A8XX-">
		<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
	</array>

	<bitset name="a6xx_cp_context_switch_cntl" inline="yes">
		<bitfield name="STOP" pos="0" type="boolean"/>
		<bitfield name="LEVEL" low="6" high="7"/>
		<bitfield name="USES_GMEM" pos="8" type="boolean"/>
		<bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/>
	</bitset>

	<reg32 offset="0x08a0" name="CP_CONTEXT_SWITCH_CNTL" type="a6xx_cp_context_switch_cntl" variants="A6XX-A7XX"/>
	<reg32 offset="0x08c0" name="CP_CONTEXT_SWITCH_CNTL" type="a6xx_cp_context_switch_cntl" variants="A8XX-"/>

	<reg64 offset="0x08a1" name="CP_CONTEXT_SWITCH_SMMU_INFO" variants="A6XX-A7XX"/>
	<reg64 offset="0x08a3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR" variants="A6XX-A7XX"/>
	<reg64 offset="0x08a5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR" variants="A6XX-A7XX"/>
	<reg64 offset="0x08a7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR" variants="A6XX-A7XX"/>
	<reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX"/>

	<reg64 offset="0x08c1" name="CP_CONTEXT_SWITCH_SMMU_INFO" variants="A8XX-"/>
	<reg64 offset="0x08c3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR" variants="A8XX-"/>
	<reg64 offset="0x08c5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR" variants="A8XX-"/>
	<reg64 offset="0x08c7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR" variants="A8XX-"/>
	<reg32 offset="0x08cb" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A8XX-"/>

	<array offset="0x08d0" name="CP_PERFCTR_CP_SEL" stride="1" length="14" variants="A6XX-A7XX"/>
	<array offset="0x08d0" name="CP_PERFCTR_CP_SEL" stride="1" length="21" variants="A8XX-"/>
	<array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX"/>

Annotation

Detected declarations: `function buffer`, `function direction`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: atlas-only.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.