drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml
Extension: .xml
Size: 10053 bytes
Lines: 217
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: drivers/gpu
Status: atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>
<import file="adreno/adreno_common.xml"/>
<import file="adreno/adreno_pm4.xml"/>

<enum name="a7xx_statetype_id">
	<value value="0" name="A7XX_TP0_NCTX_REG"/>
	<value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/>
	<value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/>
	<value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/>
	<value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/>
	<value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/>
	<value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/>
	<value value="9" name="A7XX_TP0_TMO_DATA"/>
	<value value="10" name="A7XX_TP0_SMO_DATA"/>
	<value value="11" name="A7XX_TP0_MIPMAP_BASE_DATA"/>
	<value value="32" name="A7XX_SP_NCTX_REG"/>
	<value value="33" name="A7XX_SP_CTX0_3D_CVS_REG"/>
	<value value="34" name="A7XX_SP_CTX0_3D_CPS_REG"/>
	<value value="35" name="A7XX_SP_CTX1_3D_CVS_REG"/>
	<value value="36" name="A7XX_SP_CTX1_3D_CPS_REG"/>
	<value value="37" name="A7XX_SP_CTX2_3D_CPS_REG"/>
	<value value="38" name="A7XX_SP_CTX3_3D_CPS_REG"/>
	<value value="39" name="A7XX_SP_INST_DATA"/>
	<value value="40" name="A7XX_SP_INST_DATA_1"/>
	<value value="41" name="A7XX_SP_LB_0_DATA"/>
	<value value="42" name="A7XX_SP_LB_1_DATA"/>
	<value value="43" name="A7XX_SP_LB_2_DATA"/>
	<value value="44" name="A7XX_SP_LB_3_DATA"/>
	<value value="45" name="A7XX_SP_LB_4_DATA"/>
	<value value="46" name="A7XX_SP_LB_5_DATA"/>
	<value value="47" name="A7XX_SP_LB_6_DATA"/>
	<value value="48" name="A7XX_SP_LB_7_DATA"/>
	<value value="49" name="A7XX_SP_CB_RAM"/>
	<value value="50" name="A7XX_SP_LB_13_DATA"/>
	<value value="51" name="A7XX_SP_LB_14_DATA"/>
	<value value="52" name="A7XX_SP_INST_TAG"/>
	<value value="53" name="A7XX_SP_INST_DATA_2"/>
	<value value="54" name="A7XX_SP_TMO_TAG"/>
	<value value="55" name="A7XX_SP_SMO_TAG"/>
	<value value="56" name="A7XX_SP_STATE_DATA"/>
	<value value="57" name="A7XX_SP_HWAVE_RAM"/>
	<value value="58" name="A7XX_SP_L0_INST_BUF"/>
	<value value="59" name="A7XX_SP_LB_8_DATA"/>
	<value value="60" name="A7XX_SP_LB_9_DATA"/>
	<value value="61" name="A7XX_SP_LB_10_DATA"/>
	<value value="62" name="A7XX_SP_LB_11_DATA"/>
	<value value="63" name="A7XX_SP_LB_12_DATA"/>
	<value value="64" name="A7XX_HLSQ_DATAPATH_DSTR_META"/>
	<value value="67" name="A7XX_HLSQ_L2STC_TAG_RAM"/>
	<value value="68" name="A7XX_HLSQ_L2STC_INFO_CMD"/>
	<value value="69" name="A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/>
	<value value="70" name="A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/>
	<value value="71" name="A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/>
	<value value="72" name="A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/>
	<value value="73" name="A7XX_HLSQ_CHUNK_CVS_RAM"/>
	<value value="74" name="A7XX_HLSQ_CHUNK_CPS_RAM"/>
	<value value="75" name="A7XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
	<value value="76" name="A7XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
	<value value="77" name="A7XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
	<value value="78" name="A7XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
	<value value="79" name="A7XX_HLSQ_CVS_MISC_RAM"/>
	<value value="80" name="A7XX_HLSQ_CPS_MISC_RAM"/>
	<value value="81" name="A7XX_HLSQ_CPS_MISC_RAM_1"/>
	<value value="82" name="A7XX_HLSQ_INST_RAM"/>
	<value value="83" name="A7XX_HLSQ_GFX_CVS_CONST_RAM"/>
	<value value="84" name="A7XX_HLSQ_GFX_CPS_CONST_RAM"/>

Annotation

Atlas domain: Driver Families / drivers/gpu.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.