drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml
Extension: .xml
Size: 115927 bytes
Lines: 1930
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: drivers/gpu
Status: atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>
<import file="adreno/adreno_common.xml"/>
<import file="adreno/adreno_pm4.xml"/>

<enum name="a8xx_cp_perfcounter_select">
	<value value="0" name="A8XX_PERF_CP_NEVER_COUNT"/>
	<value value="1" name="A8XX_PERF_CP_ALWAYS_COUNT"/>
	<value value="2" name="A8XX_PERF_CP_BUSY_GFX_CORE_IDLE"/>
	<value value="3" name="A8XX_PERF_CP_BUSY_CYCLES"/>
	<value value="4" name="A8XX_PERF_CP_NUM_PREEMPTIONS"/>
	<value value="5" name="A8XX_PERF_CP_PREEMPTION_REACTION_DELAY"/>
	<value value="6" name="A8XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
	<value value="7" name="A8XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
	<value value="8" name="A8XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
	<value value="9" name="A8XX_PERF_CP_PREDICATED_DRAWS_KILLED"/>
	<value value="10" name="A8XX_PERF_CP_MODE_SWITCH"/>
	<value value="11" name="A8XX_PERF_CP_ZPASS_DONE"/>
	<value value="12" name="A8XX_PERF_CP_CONTEXT_DONE"/>
	<value value="13" name="A8XX_PERF_CP_CACHE_FLUSH"/>
	<value value="14" name="A8XX_PERF_CP_LONG_PREEMPTIONS"/>
	<value value="15" name="A8XX_PERF_CP_SQE_I_CACHE_STARVE"/>
	<value value="16" name="A8XX_PERF_CP_SQE_IDLE"/>
	<value value="17" name="A8XX_PERF_CP_SQE_PM4_STARVE_RB"/>
	<value value="18" name="A8XX_PERF_CP_SQE_PM4_STARVE_IB1"/>
	<value value="19" name="A8XX_PERF_CP_SQE_PM4_STARVE_IB2"/>
	<value value="20" name="A8XX_PERF_CP_SQE_PM4_STARVE_IB3"/>
	<value value="21" name="A8XX_PERF_CP_SQE_PM4_STARVE_FSDT"/>
	<value value="22" name="A8XX_PERF_CP_SQE_PM4_STARVE_SDS"/>
	<value value="23" name="A8XX_PERF_CP_SQE_MRB_STARVE"/>
	<value value="24" name="A8XX_PERF_CP_SQE_RRB_STARVE"/>
	<value value="25" name="A8XX_PERF_CP_SQE_VSD_STARVE"/>
	<value value="26" name="A8XX_PERF_CP_VSD_DECODE_STARVE"/>
	<value value="27" name="A8XX_PERF_CP_SQE_PIPE_OUT_STALL"/>
	<value value="28" name="A8XX_PERF_CP_SQE_SYNC_STALL"/>
	<value value="29" name="A8XX_PERF_CP_SQE_PM4_WFI_STALL"/>
	<value value="30" name="A8XX_PERF_CP_SQE_SYS_WFI_STALL"/>
	<value value="31" name="A8XX_PERF_CP_WAIT_ON_OTHER_PIPE"/>
	<value value="32" name="A8XX_PERF_CP_OUTPUT_BLOCKED"/>
	<value value="33" name="A8XX_PERF_CP_SQE_T4_EXEC"/>
	<value value="34" name="A8XX_PERF_CP_SQE_LOAD_STATE_EXEC"/>
	<value value="35" name="A8XX_PERF_CP_SQE_SAVE_SDS_STATE"/>
	<value value="36" name="A8XX_PERF_CP_SQE_DRAW_EXEC"/>
	<value value="37" name="A8XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
	<value value="38" name="A8XX_PERF_CP_SQE_EXEC_PROFILED"/>
	<value value="39" name="A8XX_PERF_CP_MEMORY_POOL_EMPTY"/>
	<value value="40" name="A8XX_PERF_CP_MEMORY_POOL_SYNC_STALL"/>
	<value value="41" name="A8XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
	<value value="42" name="A8XX_PERF_CP_MEMORY_POOL_BELOW_THRESH"/>
	<value value="43" name="A8XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
	<value value="44" name="A8XX_PERF_CP_AHB_STALL_SQE_GMU"/>
	<value value="45" name="A8XX_PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
	<value value="46" name="A8XX_PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
	<value value="47" name="A8XX_PERF_CP_CLUSTER_FE_U_EMPTY"/>
	<value value="48" name="A8XX_PERF_CP_CLUSTER_FE_S_EMPTY"/>
	<value value="49" name="A8XX_PERF_CP_CLUSTER_SP_VS_EMPTY"/>
	<value value="50" name="A8XX_PERF_CP_CLUSTER_VPC_US_EMPTY"/>
	<value value="51" name="A8XX_PERF_CP_CLUSTER_VPC_VS_EMPTY"/>
	<value value="52" name="A8XX_PERF_CP_CLUSTER_GRAS_EMPTY"/>
	<value value="53" name="A8XX_PERF_CP_CLUSTER_SP_PS_EMPTY"/>
	<value value="54" name="A8XX_PERF_CP_CLUSTER_VPC_PS_EMPTY"/>
	<value value="55" name="A8XX_PERF_CP_CLUSTER_PS_EMPTY"/>
	<value value="56" name="A8XX_PERF_CP_PM4_DATA"/>
	<value value="57" name="A8XX_PERF_CP_PM4_HEADERS"/>
	<value value="58" name="A8XX_PERF_CP_VBIF_READ_BEATS"/>
	<value value="59" name="A8XX_PERF_CP_VBIF_WRITE_BEATS"/>
	<value value="60" name="A8XX_PERF_CP_SQE_INSTR_COUNTER"/>

Annotation

Atlas domain: Driver Families / drivers/gpu.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.