drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
Extension
.xml
Size
94755 bytes
Lines
2448
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: drivers/gpu
Status
atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>
<import file="adreno/adreno_common.xml"/>

<enum name="vgt_event_type" varset="chip">
	<value name="VS_DEALLOC" value="0x00" variants="A2XX-A5XX"/>
	<value name="PS_DEALLOC" value="0x01" variants="A2XX-A5XX"/>
	<value name="VS_DONE_TS" value="0x02" variants="A2XX-A5XX"/>
	<value name="PS_DONE_TS" value="0x03" variants="A2XX-A5XX"/>
	<doc>
		Flushes dirty data from UCHE, and also writes a GPU timestamp to
		the address if one is provided.
	</doc>
	<value name="CACHE_FLUSH_TS" value="0x04"/>
	<value name="CONTEXT_DONE" value="0x05"/>
	<value name="CACHE_FLUSH" value="0x06" variants="A2XX-A4XX"/>
	<value name="VIZQUERY_START" value="0x07" variants="A2XX"/>
	<value name="HLSQ_FLUSH" value="0x07" variants="A3XX-A4XX"/>
	<value name="VIZQUERY_END" value="0x08" variants="A2XX"/>
	<value name="SC_WAIT_WC" value="0x09" variants="A2XX"/>
	<value name="WRITE_PRIMITIVE_COUNTS" value="0x09" variants="A6XX-"/>
	<value name="START_PRIMITIVE_CTRS" value="0x0b" variants="A6XX-"/>
	<value name="STOP_PRIMITIVE_CTRS" value="0x0c" variants="A6XX-"/>
	<!-- Not sure that these 4 events don't have the same meaning as on A5XX+ -->
	<value name="RST_PIX_CNT" value="0x0d" variants="A2XX-A4XX"/>
	<value name="RST_VTX_CNT" value="0x0e" variants="A2XX-A4XX"/>
	<value name="TILE_FLUSH" value="0x0f" variants="A2XX-A4XX"/>
	<value name="STAT_EVENT" value="0x10" variants="A2XX-A4XX"/>
	<value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="0x14" variants="A2XX-A4XX"/>
	<doc>
		If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed
		sample counts to RB_SAMPLE_COUNTER_BASE.  This writes to main
		memory, skipping UCHE.
	</doc>
	<value name="ZPASS_DONE" value="0x15"/>
	<value name="CACHE_FLUSH_AND_INV_EVENT" value="0x16" variants="A2XX"/>

	<doc>
		Writes the GPU timestamp to the address that follows, once RB
		access and flushes are complete.
	</doc>
	<value name="RB_DONE_TS" value="0x16" variants="A3XX-"/>

	<value name="PERFCOUNTER_START" value="0x17" variants="A2XX-A4XX"/>
	<value name="PERFCOUNTER_STOP" value="0x18" variants="A2XX-A4XX"/>
	<value name="VS_FETCH_DONE" value="0x1b" variants="A2XX-A5XX"/>
	<value name="FACENESS_FLUSH" value="0x1c" variants="A2XX-A4XX"/>

	<!-- a5xx events -->
	<value name="WT_DONE_TS" value="0x08" variants="A5XX-A6XX"/>
	<value name="START_FRAGMENT_CTRS" value="0x0d" variants="A5XX-"/>
	<value name="STOP_FRAGMENT_CTRS" value="0x0e" variants="A5XX-"/>
	<value name="START_COMPUTE_CTRS" value="0x0f" variants="A5XX-"/>
	<value name="STOP_COMPUTE_CTRS" value="0x10" variants="A5XX-"/>
	<value name="FLUSH_SO_0" value="0x11" variants="A5XX-"/>
	<value name="FLUSH_SO_1" value="0x12" variants="A5XX-"/>
	<value name="FLUSH_SO_2" value="0x13" variants="A5XX-"/>
	<value name="FLUSH_SO_3" value="0x14" variants="A5XX-"/>

	<doc>
		Invalidates depth attachment data from the CCU.  We assume this
		happens in the last stage.
	</doc>
	<value name="PC_CCU_INVALIDATE_DEPTH" value="0x18" variants="A5XX-A6XX"/>

	<doc>
		Invalidates color attachment data from the CCU.  We assume this

Annotation

Implementation Notes