drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml
Extension
.xml
Size
5391 bytes
Lines
136
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: drivers/gpu
Status
atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>

<domain name="DSI_14nm_PHY_CMN" width="32">
	<reg32 offset="0x00000" name="REVISION_ID0"/>
	<reg32 offset="0x00004" name="REVISION_ID1"/>
	<reg32 offset="0x00008" name="REVISION_ID2"/>
	<reg32 offset="0x0000c" name="REVISION_ID3"/>
	<reg32 offset="0x00010" name="CLK_CFG0">
		<bitfield name="DIV_CTRL_3_0" low="4" high="7" type="uint"/>
		<bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>
	</reg32>
	<reg32 offset="0x00014" name="CLK_CFG1">
		<bitfield name="DSICLK_SEL" pos="0" type="boolean"/>
	</reg32>
	<reg32 offset="0x00018" name="GLBL_TEST_CTRL">
		<bitfield name="BITCLK_HS_SEL" pos="2" type="boolean"/>
	</reg32>
	<reg32 offset="0x0001C" name="CTRL_0"/>
	<reg32 offset="0x00020" name="CTRL_1">
	</reg32>
	<reg32 offset="0x00024" name="HW_TRIGGER"/>
	<reg32 offset="0x00028" name="SW_CFG0"/>
	<reg32 offset="0x0002C" name="SW_CFG1"/>
	<reg32 offset="0x00030" name="SW_CFG2"/>
	<reg32 offset="0x00034" name="HW_CFG0"/>
	<reg32 offset="0x00038" name="HW_CFG1"/>
	<reg32 offset="0x0003C" name="HW_CFG2"/>
	<reg32 offset="0x00040" name="HW_CFG3"/>
	<reg32 offset="0x00044" name="HW_CFG4"/>
	<reg32 offset="0x00048" name="PLL_CNTRL">
		<bitfield name="PLL_START" pos="0" type="boolean"/>
	</reg32>
	<reg32 offset="0x0004C" name="LDO_CNTRL">
		<bitfield name="VREG_CTRL" low="0" high="5" type="uint"/>
	</reg32>
</domain>

<domain name="DSI_14nm_PHY" width="32">
	<array offset="0x00000" name="LN" length="5" stride="0x80">
		<reg32 offset="0x00" name="CFG0">
			<bitfield name="PREPARE_DLY" low="6" high="7" type="uint"/>
		</reg32>
		<reg32 offset="0x04" name="CFG1">
			<bitfield name="HALFBYTECLK_EN" pos="0" type="boolean"/>
		</reg32>
		<reg32 offset="0x08" name="CFG2"/>
		<reg32 offset="0x0c" name="CFG3"/>
		<reg32 offset="0x10" name="TEST_DATAPATH"/>
		<reg32 offset="0x14" name="TEST_STR"/>
		<reg32 offset="0x18" name="TIMING_CTRL_4">
			<bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
		</reg32>
		<reg32 offset="0x1c" name="TIMING_CTRL_5">
			<bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
		</reg32>
		<reg32 offset="0x20" name="TIMING_CTRL_6">
			<bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
		</reg32>
		<reg32 offset="0x24" name="TIMING_CTRL_7">
			<bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
		</reg32>
		<reg32 offset="0x28" name="TIMING_CTRL_8">
			<bitfield name="HS_RQST" low="0" high="7" type="uint"/>
		</reg32>
		<reg32 offset="0x2c" name="TIMING_CTRL_9">
			<bitfield name="TA_GO" low="0" high="2" type="uint"/>

Annotation

Implementation Notes