drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
Extension
.xml
Size
12471 bytes
Lines
262
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: drivers/gpu
Status
atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>

<domain name="DSI_7nm_PHY_CMN" width="32">
	<reg32 offset="0x00000" name="REVISION_ID0"/>
	<reg32 offset="0x00004" name="REVISION_ID1"/>
	<reg32 offset="0x00008" name="REVISION_ID2"/>
	<reg32 offset="0x0000c" name="REVISION_ID3"/>
	<reg32 offset="0x00010" name="CLK_CFG0">
		<bitfield name="DIV_CTRL_3_0" low="0" high="3" type="uint"/>
		<bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>
	</reg32>
	<reg32 offset="0x00014" name="CLK_CFG1">
		<bitfield name="CLK_EN" pos="5" type="boolean"/>
		<bitfield name="CLK_EN_SEL" pos="4" type="boolean"/>
		<bitfield name="BITCLK_SEL" low="2" high="3" type="uint"/>
		<bitfield name="DSICLK_SEL" low="0" high="1" type="uint"/>
	</reg32>
	<reg32 offset="0x00018" name="GLBL_CTRL"/>
	<reg32 offset="0x0001c" name="RBUF_CTRL"/>
	<reg32 offset="0x00020" name="VREG_CTRL_0"/>
	<reg32 offset="0x00024" name="CTRL_0">
		<bitfield name="CLKSL_SHUTDOWNB" pos="7" type="boolean"/>
		<bitfield name="DIGTOP_PWRDN_B" pos="6" type="boolean"/>
		<bitfield name="PLL_SHUTDOWNB" pos="5" type="boolean"/>
		<bitfield name="DLN3_SHUTDOWNB" pos="4" type="boolean"/>
		<bitfield name="DLN2_SHUTDOWNB" pos="3" type="boolean"/>
		<bitfield name="CLK_SHUTDOWNB" pos="2" type="boolean"/>
		<bitfield name="DLN1_SHUTDOWNB" pos="1" type="boolean"/>
		<bitfield name="DLN0_SHUTDOWNB" pos="0" type="boolean"/>
	</reg32>
	<reg32 offset="0x00028" name="CTRL_1"/>
	<reg32 offset="0x0002c" name="CTRL_2"/>
	<reg32 offset="0x00030" name="CTRL_3"/>
	<reg32 offset="0x001b0" name="CTRL_5"/>
	<reg32 offset="0x00034" name="LANE_CFG0"/>
	<reg32 offset="0x00038" name="LANE_CFG1"/>
	<reg32 offset="0x0003c" name="PLL_CNTRL"/>
	<reg32 offset="0x00040" name="DPHY_SOT"/>
	<reg32 offset="0x000a0" name="LANE_CTRL0"/>
	<reg32 offset="0x000a4" name="LANE_CTRL1"/>
	<reg32 offset="0x000a8" name="LANE_CTRL2"/>
	<reg32 offset="0x000ac" name="LANE_CTRL3"/>
	<reg32 offset="0x000b0" name="LANE_CTRL4"/>
	<reg32 offset="0x000b4" name="TIMING_CTRL_0"/>
	<reg32 offset="0x000b8" name="TIMING_CTRL_1"/>
	<reg32 offset="0x000bc" name="TIMING_CTRL_2"/>
	<reg32 offset="0x000c0" name="TIMING_CTRL_3"/>
	<reg32 offset="0x000c4" name="TIMING_CTRL_4"/>
	<reg32 offset="0x000c8" name="TIMING_CTRL_5"/>
	<reg32 offset="0x000cc" name="TIMING_CTRL_6"/>
	<reg32 offset="0x000d0" name="TIMING_CTRL_7"/>
	<reg32 offset="0x000d4" name="TIMING_CTRL_8"/>
	<reg32 offset="0x000d8" name="TIMING_CTRL_9"/>
	<reg32 offset="0x000dc" name="TIMING_CTRL_10"/>
	<reg32 offset="0x000e0" name="TIMING_CTRL_11"/>
	<reg32 offset="0x000e4" name="TIMING_CTRL_12"/>
	<reg32 offset="0x000e8" name="TIMING_CTRL_13"/>
	<reg32 offset="0x000ec" name="GLBL_HSTX_STR_CTRL_0"/>
	<reg32 offset="0x000f0" name="GLBL_HSTX_STR_CTRL_1"/>
	<reg32 offset="0x000f4" name="GLBL_RESCODE_OFFSET_TOP_CTRL"/>
	<reg32 offset="0x000f8" name="GLBL_RESCODE_OFFSET_BOT_CTRL"/>
	<reg32 offset="0x000fc" name="GLBL_RESCODE_OFFSET_MID_CTRL"/>
	<reg32 offset="0x00100" name="GLBL_LPTX_STR_CTRL"/>
	<reg32 offset="0x00104" name="GLBL_PEMPH_CTRL_0"/>
	<reg32 offset="0x00108" name="GLBL_PEMPH_CTRL_1"/>
	<reg32 offset="0x0010c" name="GLBL_STR_SWI_CAL_SEL_CTRL"/>

Annotation

Implementation Notes