drivers/gpu/drm/msm/registers/display/edp.xml

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/msm/registers/display/edp.xml

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/msm/registers/display/edp.xml
Extension
.xml
Size
10426 bytes
Lines
240
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: drivers/gpu
Status
atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>

<domain name="EDP" width="32">
	<enum name="edp_color_depth">
		<value name="EDP_6BIT"  value="0"/>
		<value name="EDP_8BIT"  value="1"/>
		<value name="EDP_10BIT" value="2"/>
		<value name="EDP_12BIT" value="3"/>
		<value name="EDP_16BIT" value="4"/>
	</enum>

	<enum name="edp_component_format">
		<value name="EDP_RGB" value="0"/>
		<value name="EDP_YUV422" value="1"/>
		<value name="EDP_YUV444" value="2"/>
	</enum>

	<reg32 offset="0x0004" name="MAINLINK_CTRL">
		<bitfield name="ENABLE" pos="0" type="boolean"/>
		<bitfield name="RESET"  pos="1" type="boolean"/>
	</reg32>

	<reg32 offset="0x0008" name="STATE_CTRL">
		<bitfield name="TRAIN_PATTERN_1"       pos="0" type="boolean"/>
		<bitfield name="TRAIN_PATTERN_2"       pos="1" type="boolean"/>
		<bitfield name="TRAIN_PATTERN_3"       pos="2" type="boolean"/>
		<bitfield name="SYMBOL_ERR_RATE_MEAS"  pos="3" type="boolean"/>
		<bitfield name="PRBS7"                 pos="4" type="boolean"/>
		<bitfield name="CUSTOM_80_BIT_PATTERN" pos="5" type="boolean"/>
		<bitfield name="SEND_VIDEO"            pos="6" type="boolean"/>
		<bitfield name="PUSH_IDLE"             pos="7" type="boolean"/>
	</reg32>

	<reg32 offset="0x000c" name="CONFIGURATION_CTRL">
		<!-- next two may be swapped? -->
		<bitfield name="SYNC_CLK" pos="0" type="boolean"/>
		<bitfield name="STATIC_MVID" pos="1" type="boolean"/>
		<bitfield name="PROGRESSIVE" pos="2" type="boolean"/>
		<!-- # of lanes minus one: -->
		<bitfield name="LANES" low="4" high="5" type="uint"/>
		<bitfield name="ENHANCED_FRAMING" pos="6" type="boolean"/>
		<!--
		   NOTE: only 6bit and 8bit valid
		 -->
		<bitfield name="COLOR" pos="8" type="edp_color_depth"/>
	</reg32>

	<reg32 offset="0x0014" name="SOFTWARE_MVID" type="uint"/>
	<reg32 offset="0x0018" name="SOFTWARE_NVID" type="uint"/>

	<reg32 offset="0x001c" name="TOTAL_HOR_VER">
		<bitfield name="HORIZ" low="0" high="15" type="uint"/>
		<bitfield name="VERT"  low="16" high="31" type="uint"/>
	</reg32>

	<reg32 offset="0x0020" name="START_HOR_VER_FROM_SYNC">
		<bitfield name="HORIZ" low="0" high="15" type="uint"/>
		<bitfield name="VERT"  low="16" high="31" type="uint"/>
	</reg32>

	<reg32 offset="0x0024" name="HSYNC_VSYNC_WIDTH_POLARITY">
		<bitfield name="HORIZ"  low="0" high="14" type="uint"/>
		<bitfield name="NHSYNC" pos="15" type="boolean"/>
		<bitfield name="VERT"   low="16" high="30" type="uint"/>
		<bitfield name="NVSYNC" pos="31" type="boolean"/>
	</reg32>

Annotation

Implementation Notes