drivers/gpu/drm/msm/registers/display/sfpb.xml

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/msm/registers/display/sfpb.xml

Extension

.xml

Size

612 bytes

Lines

18

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: drivers/gpu

Status

atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>

<domain name="SFPB" width="32">
	<enum name="sfpb_ahb_arb_master_port_en">
		<value name="SFPB_MASTER_PORT_ENABLE" value="3"/>
		<value name="SFPB_MASTER_PORT_DISABLE" value="0"/>
	</enum>
	<reg32 offset="0x0058" name="GPREG">
		<bitfield name="MASTER_PORT_EN" low="11" high="12" type="sfpb_ahb_arb_master_port_en"/>
	</reg32>
</domain>

</database>

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.