drivers/gpu/drm/nouveau/dispnv50/atom.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/dispnv50/atom.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/dispnv50/atom.h
Extension
.h
Size
4109 bytes
Lines
281
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct nv50_atom {
	struct drm_atomic_commit state;

	struct list_head outp;
	bool lock_core;
	bool flush_disable;
};

#define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)

struct nv50_head_atom {
	struct drm_crtc_state state;

	struct {
		u32 mask;
		u32 owned;
		u32 olut;
	} wndw;

	struct {
		u16 iW;
		u16 iH;
		u16 oW;
		u16 oH;
	} view;

	struct nv50_head_mode {
		bool interlace;
		u32 clock;
		struct {
			u16 active;
			u16 synce;
			u16 blanke;
			u16 blanks;
		} h;
		struct {
			u32 active;
			u16 synce;
			u16 blanke;
			u16 blanks;
			u16 blank2s;
			u16 blank2e;
			u16 blankus;
		} v;
	} mode;

	struct {
		bool visible;
		u32 handle;
		u64 offset:40;
		u8 buffer:1;
		u8 mode:4;
		u16 size:11;
		u8 range:2;
		u8 output_mode:2;
		void (*load)(struct drm_color_lut *, int size, void __iomem *);
	} olut;

	struct {
		bool visible;
		u32 handle;
		u64 offset:40;
		u8  format;
		u8  kind:7;
		u8  layout:1;
		u8  blockh:4;
		u16 blocks:12;
		u32 pitch:20;
		u16 x;
		u16 y;
		u16 w;
		u16 h;
	} core;

	struct {
		bool visible;
		u32 handle;
		u64 offset:40;
		u8  layout:2;
		u8  format:8;
	} curs;

	struct {
		u8  depth;
		u8  cpp;
		u16 x;
		u16 y;
		u16 w;
		u16 h;
	} base;

Annotation

Implementation Notes