drivers/gpu/drm/nouveau/include/nvfw/fw.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/nouveau/include/nvfw/fw.h

Extension

.h

Size

532 bytes

Lines

29

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• core/os.h

Detected Declarations

• struct nvkm_subdev
• struct nvfw_bin_hdr
• struct nvfw_bl_desc

Annotated Snippet

struct nvfw_bin_hdr {
	u32 bin_magic;
	u32 bin_ver;
	u32 bin_size;
	u32 header_offset;
	u32 data_offset;
	u32 data_size;
};

const struct nvfw_bin_hdr *nvfw_bin_hdr(struct nvkm_subdev *, const void *);

struct nvfw_bl_desc {
	u32 start_tag;
	u32 dmem_load_off;
	u32 code_off;
	u32 code_size;
	u32 data_off;
	u32 data_size;
};

const struct nvfw_bl_desc *nvfw_bl_desc(struct nvkm_subdev *, const void *);
#endif

Annotation

• Immediate include surface: `core/os.h`.
• Detected declarations: `struct nvkm_subdev`, `struct nvfw_bin_hdr`, `struct nvfw_bl_desc`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.