drivers/gpu/drm/nouveau/include/nvhw/class/cl502d.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/include/nvhw/class/cl502d.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/nouveau/include/nvhw/class/cl502d.h- Extension
.h- Size
- 29910 bytes
- Lines
- 338
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _cl_nv50_twod_h_
#define _cl_nv50_twod_h_
#define NV502D_SET_OBJECT 0x0000
#define NV502D_SET_OBJECT_POINTER 15:0
#define NV502D_WAIT_FOR_IDLE 0x0110
#define NV502D_WAIT_FOR_IDLE_V 31:0
#define NV502D_SET_DST_CONTEXT_DMA 0x0184
#define NV502D_SET_DST_CONTEXT_DMA_HANDLE 31:0
#define NV502D_SET_SRC_CONTEXT_DMA 0x0188
#define NV502D_SET_SRC_CONTEXT_DMA_HANDLE 31:0
#define NV502D_SET_SEMAPHORE_CONTEXT_DMA 0x018c
#define NV502D_SET_SEMAPHORE_CONTEXT_DMA_HANDLE 31:0
#define NV502D_SET_DST_FORMAT 0x0200
#define NV502D_SET_DST_FORMAT_V 7:0
#define NV502D_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
#define NV502D_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
#define NV502D_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
#define NV502D_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5
#define NV502D_SET_DST_FORMAT_V_A8BL8GL8RL8 0x000000D6
#define NV502D_SET_DST_FORMAT_V_A2B10G10R10 0x000000D1
#define NV502D_SET_DST_FORMAT_V_X8R8G8B8 0x000000E6
#define NV502D_SET_DST_FORMAT_V_X8RL8GL8BL8 0x000000E7
#define NV502D_SET_DST_FORMAT_V_X8B8G8R8 0x000000F9
#define NV502D_SET_DST_FORMAT_V_X8BL8GL8RL8 0x000000FA
#define NV502D_SET_DST_FORMAT_V_R5G6B5 0x000000E8
#define NV502D_SET_DST_FORMAT_V_A1R5G5B5 0x000000E9
#define NV502D_SET_DST_FORMAT_V_X1R5G5B5 0x000000F8
#define NV502D_SET_DST_FORMAT_V_Y8 0x000000F3
#define NV502D_SET_DST_FORMAT_V_Y16 0x000000EE
#define NV502D_SET_DST_FORMAT_V_Y32 0x000000FF
#define NV502D_SET_DST_FORMAT_V_Z1R5G5B5 0x000000FB
#define NV502D_SET_DST_FORMAT_V_O1R5G5B5 0x000000FC
#define NV502D_SET_DST_FORMAT_V_Z8R8G8B8 0x000000FD
#define NV502D_SET_DST_FORMAT_V_O8R8G8B8 0x000000FE
#define NV502D_SET_DST_FORMAT_V_Y1_8X8 0x0000001C
#define NV502D_SET_DST_FORMAT_V_RF16 0x000000F2
#define NV502D_SET_DST_FORMAT_V_RF32 0x000000E5
#define NV502D_SET_DST_FORMAT_V_RF32_GF32 0x000000CB
#define NV502D_SET_DST_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA
#define NV502D_SET_DST_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE
#define NV502D_SET_DST_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0
#define NV502D_SET_DST_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3
#define NV502D_SET_DST_MEMORY_LAYOUT 0x0204
#define NV502D_SET_DST_MEMORY_LAYOUT_V 0:0
#define NV502D_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000
#define NV502D_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001
#define NV502D_SET_DST_PITCH 0x0214
#define NV502D_SET_DST_PITCH_V 31:0
#define NV502D_SET_DST_WIDTH 0x0218
#define NV502D_SET_DST_WIDTH_V 31:0
#define NV502D_SET_DST_HEIGHT 0x021c
#define NV502D_SET_DST_HEIGHT_V 31:0
#define NV502D_SET_DST_OFFSET_UPPER 0x0220
#define NV502D_SET_DST_OFFSET_UPPER_V 7:0
#define NV502D_SET_DST_OFFSET_LOWER 0x0224
#define NV502D_SET_DST_OFFSET_LOWER_V 31:0
#define NV502D_SET_SRC_FORMAT 0x0230
#define NV502D_SET_SRC_FORMAT_V 7:0
#define NV502D_SET_SRC_FORMAT_V_A8R8G8B8 0x000000CF
#define NV502D_SET_SRC_FORMAT_V_A8RL8GL8BL8 0x000000D0
#define NV502D_SET_SRC_FORMAT_V_A2R10G10B10 0x000000DF
#define NV502D_SET_SRC_FORMAT_V_A8B8G8R8 0x000000D5
#define NV502D_SET_SRC_FORMAT_V_A8BL8GL8RL8 0x000000D6
#define NV502D_SET_SRC_FORMAT_V_A2B10G10R10 0x000000D1
#define NV502D_SET_SRC_FORMAT_V_X8R8G8B8 0x000000E6
#define NV502D_SET_SRC_FORMAT_V_X8RL8GL8BL8 0x000000E7
#define NV502D_SET_SRC_FORMAT_V_X8B8G8R8 0x000000F9
#define NV502D_SET_SRC_FORMAT_V_X8BL8GL8RL8 0x000000FA
#define NV502D_SET_SRC_FORMAT_V_R5G6B5 0x000000E8
#define NV502D_SET_SRC_FORMAT_V_A1R5G5B5 0x000000E9
#define NV502D_SET_SRC_FORMAT_V_X1R5G5B5 0x000000F8
#define NV502D_SET_SRC_FORMAT_V_Y8 0x000000F3
#define NV502D_SET_SRC_FORMAT_V_AY8 0x0000001D
#define NV502D_SET_SRC_FORMAT_V_Y16 0x000000EE
#define NV502D_SET_SRC_FORMAT_V_Y32 0x000000FF
#define NV502D_SET_SRC_FORMAT_V_Z1R5G5B5 0x000000FB
#define NV502D_SET_SRC_FORMAT_V_O1R5G5B5 0x000000FCAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.