drivers/gpu/drm/nouveau/include/nvhw/class/cl887d.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/include/nvhw/class/cl887d.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/nouveau/include/nvhw/class/cl887d.h
Extension: .h
Size: 4989 bytes
Lines: 69
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _cl887d_h_
#define _cl887d_h_

#define NV887D_SOR_SET_CONTROL(a)                                               (0x00000600 + (a)*0x00000040)
#define NV887D_SOR_SET_CONTROL_OWNER                                            3:0
#define NV887D_SOR_SET_CONTROL_OWNER_NONE                                       (0x00000000)
#define NV887D_SOR_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
#define NV887D_SOR_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
#define NV887D_SOR_SET_CONTROL_SUB_OWNER                                        5:4
#define NV887D_SOR_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
#define NV887D_SOR_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
#define NV887D_SOR_SET_CONTROL_PROTOCOL                                         11:8
#define NV887D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB                          (0x00000003)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS                        (0x00000004)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT                                 (0x00000007)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY                                   12:12
#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY                                   13:13
#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH                                      19:16
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                              (0x00000000)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                           (0x00000001)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                           (0x00000002)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                           (0x00000003)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                           (0x00000004)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                           (0x00000005)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                           (0x00000006)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                           (0x00000007)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                           (0x00000008)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                           (0x00000009)
#endif // _cl887d_h

Annotation

Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.