drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h

Extension

.h

Size

567 bytes

Lines

24

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• core/engine.h

Detected Declarations

• struct nvkm_xtensa
• struct nvkm_xtensa_func

Annotated Snippet

struct nvkm_xtensa {
	const struct nvkm_xtensa_func *func;
	u32 addr;
	struct nvkm_engine engine;

	struct nvkm_memory *gpu_fw;
};

int nvkm_xtensa_new_(const struct nvkm_xtensa_func *, struct nvkm_device *,
		     enum nvkm_subdev_type, int, bool enable, u32 addr, struct nvkm_engine **);

struct nvkm_xtensa_func {
	u32 fifo_val;
	u32 unkd28;
	struct nvkm_sclass sclass[];
};
#endif

Annotation

• Immediate include surface: `core/engine.h`.
• Detected declarations: `struct nvkm_xtensa`, `struct nvkm_xtensa_func`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.