drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/iccsense.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/iccsense.h

Extension

.h

Size

427 bytes

Lines

24

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• struct pwr_rail_resistor_t
• struct pwr_rail_t
• struct nvbios_iccsense

Annotated Snippet

struct pwr_rail_resistor_t {
	u8 mohm;
	bool enabled;
};

struct pwr_rail_t {
	u8 mode;
	u8 extdev_id;
	u8 resistor_count;
	struct pwr_rail_resistor_t resistors[3];
	u16 config;
};

struct nvbios_iccsense {
	int nr_entry;
	struct pwr_rail_t *rail;
};

int nvbios_iccsense_parse(struct nvkm_bios *, struct nvbios_iccsense *);
#endif

Annotation

• Detected declarations: `struct pwr_rail_resistor_t`, `struct pwr_rail_t`, `struct nvbios_iccsense`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.