drivers/gpu/drm/nouveau/nv10_fence.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nv10_fence.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/nouveau/nv10_fence.c- Extension
.c- Size
- 2883 bytes
- Lines
- 109
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
nouveau_drv.hnouveau_dma.hnv10_fence.hnvif/push006c.hnvhw/class/cl006e.h
Detected Declarations
function filesfunction nv10_fence_syncfunction nv10_fence_readfunction nv10_fence_context_delfunction nv10_fence_context_newfunction nv10_fence_destroyfunction nv10_fence_create
Annotated Snippet
#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nv10_fence.h"
#include <nvif/push006c.h>
#include <nvhw/class/cl006e.h>
int
nv10_fence_emit(struct nouveau_fence *fence)
{
struct nvif_push *push = &fence->channel->chan.push;
int ret = PUSH_WAIT(push, 2);
if (ret == 0) {
PUSH_MTHD(push, NV06E, SET_REFERENCE, fence->base.seqno);
PUSH_KICK(push);
}
return ret;
}
static int
nv10_fence_sync(struct nouveau_fence *fence,
struct nouveau_channel *prev, struct nouveau_channel *chan)
{
return -ENODEV;
}
u32
nv10_fence_read(struct nouveau_channel *chan)
{
return NVIF_RD32(&chan->user, NV06E, REFERENCE);
}
void
nv10_fence_context_del(struct nouveau_channel *chan)
{
struct nv10_fence_chan *fctx = chan->fence;
nouveau_fence_context_del(&fctx->base);
nvif_object_dtor(&fctx->sema);
chan->fence = NULL;
nouveau_fence_context_free(&fctx->base);
}
static int
nv10_fence_context_new(struct nouveau_channel *chan)
{
struct nv10_fence_chan *fctx;
fctx = chan->fence = kzalloc_obj(*fctx);
if (!fctx)
return -ENOMEM;
nouveau_fence_context_new(chan, &fctx->base);
fctx->base.emit = nv10_fence_emit;
fctx->base.read = nv10_fence_read;
fctx->base.sync = nv10_fence_sync;
return 0;
}
void
nv10_fence_destroy(struct nouveau_drm *drm)
{
struct nv10_fence_priv *priv = drm->fence;
nouveau_bo_unpin_del(&priv->bo);
drm->fence = NULL;
kfree(priv);
}
int
nv10_fence_create(struct nouveau_drm *drm)
{
struct nv10_fence_priv *priv;
priv = drm->fence = kzalloc_obj(*priv);
if (!priv)
return -ENOMEM;
priv->base.dtor = nv10_fence_destroy;
priv->base.context_new = nv10_fence_context_new;
priv->base.context_del = nv10_fence_context_del;
spin_lock_init(&priv->lock);
return 0;
}
Annotation
- Immediate include surface: `nouveau_drv.h`, `nouveau_dma.h`, `nv10_fence.h`, `nvif/push006c.h`, `nvhw/class/cl006e.h`.
- Detected declarations: `function files`, `function nv10_fence_sync`, `function nv10_fence_read`, `function nv10_fence_context_del`, `function nv10_fence_context_new`, `function nv10_fence_destroy`, `function nv10_fence_create`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.