drivers/gpu/drm/nouveau/nv17_fence.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nv17_fence.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/nv17_fence.c
Extension
.c
Size
4005 bytes
Lines
142
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nv10_fence.h"

#include <nvif/push006c.h>

#include <nvif/class.h>
#include <nvif/cl0002.h>

#include <nvhw/class/cl176e.h>

int
nv17_fence_sync(struct nouveau_fence *fence,
		struct nouveau_channel *prev, struct nouveau_channel *chan)
{
	struct nouveau_cli *cli = prev->cli;
	struct nv10_fence_priv *priv = cli->drm->fence;
	struct nv10_fence_chan *fctx = chan->fence;
	struct nvif_push *ppush = &prev->chan.push;
	struct nvif_push *npush = &chan->chan.push;
	u32 value;
	int ret;

	if (!mutex_trylock(&cli->mutex))
		return -EBUSY;

	spin_lock(&priv->lock);
	value = priv->sequence;
	priv->sequence += 2;
	spin_unlock(&priv->lock);

	ret = PUSH_WAIT(ppush, 5);
	if (!ret) {
		PUSH_MTHD(ppush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
					 SEMAPHORE_OFFSET, 0,
					 SEMAPHORE_ACQUIRE, value + 0,
					 SEMAPHORE_RELEASE, value + 1);
		PUSH_KICK(ppush);
	}

	if (!ret && !(ret = PUSH_WAIT(npush, 5))) {
		PUSH_MTHD(npush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
					 SEMAPHORE_OFFSET, 0,
					 SEMAPHORE_ACQUIRE, value + 1,
					 SEMAPHORE_RELEASE, value + 2);
		PUSH_KICK(npush);
	}

	mutex_unlock(&cli->mutex);
	return 0;
}

static int
nv17_fence_context_new(struct nouveau_channel *chan)
{
	struct nv10_fence_priv *priv = chan->cli->drm->fence;
	struct ttm_resource *reg = priv->bo->bo.resource;
	struct nv10_fence_chan *fctx;
	u32 start = reg->start * PAGE_SIZE;
	u32 limit = start + priv->bo->bo.base.size - 1;
	int ret = 0;

	fctx = chan->fence = kzalloc_obj(*fctx);
	if (!fctx)
		return -ENOMEM;

	nouveau_fence_context_new(chan, &fctx->base);
	fctx->base.emit = nv10_fence_emit;
	fctx->base.read = nv10_fence_read;
	fctx->base.sync = nv17_fence_sync;

	ret = nvif_object_ctor(&chan->user, "fenceCtxDma", NvSema,
			       NV_DMA_FROM_MEMORY,
			       &(struct nv_dma_v0) {
					.target = NV_DMA_V0_TARGET_VRAM,
					.access = NV_DMA_V0_ACCESS_RDWR,
					.start = start,
					.limit = limit,
			       }, sizeof(struct nv_dma_v0),
			       &fctx->sema);
	if (ret)
		nv10_fence_context_del(chan);
	return ret;
}

void
nv17_fence_resume(struct nouveau_drm *drm)
{
	struct nv10_fence_priv *priv = drm->fence;

Annotation

Implementation Notes