drivers/gpu/drm/nouveau/nv84_fence.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nv84_fence.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/nv84_fence.c
Extension
.c
Size
6133 bytes
Lines
229
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nouveau_fence.h"
#include "nouveau_vmm.h"

#include "nv50_display.h"

#include <nvif/push206e.h>

#include <nvhw/class/cl826f.h>

static int
nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{
	struct nvif_push *push = &chan->chan.push;
	int ret = PUSH_WAIT(push, 8);
	if (ret == 0) {
		PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);

		PUSH_MTHD(push, NV826F, SEMAPHOREA,
			  NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),

					SEMAPHOREB, lower_32_bits(virtual),
					SEMAPHOREC, sequence,

					SEMAPHORED,
			  NVDEF(NV826F, SEMAPHORED, OPERATION, RELEASE),

					NON_STALLED_INTERRUPT, 0);
		PUSH_KICK(push);
	}
	return ret;
}

static int
nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{
	struct nvif_push *push = &chan->chan.push;
	int ret = PUSH_WAIT(push, 7);
	if (ret == 0) {
		PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);

		PUSH_MTHD(push, NV826F, SEMAPHOREA,
			  NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),

					SEMAPHOREB, lower_32_bits(virtual),
					SEMAPHOREC, sequence,

					SEMAPHORED,
			  NVDEF(NV826F, SEMAPHORED, OPERATION, ACQ_GEQ));
		PUSH_KICK(push);
	}
	return ret;
}

static inline u32
nv84_fence_chid(struct nouveau_channel *chan)
{
	return chan->cli->drm->runl[chan->runlist].chan_id_base + chan->chid;
}

static int
nv84_fence_emit(struct nouveau_fence *fence)
{
	struct nouveau_channel *chan = fence->channel;
	struct nv84_fence_chan *fctx = chan->fence;
	u64 addr = fctx->vma->addr + nv84_fence_chid(chan) * 16;

	return fctx->base.emit32(chan, addr, fence->base.seqno);
}

static int
nv84_fence_sync(struct nouveau_fence *fence,
		struct nouveau_channel *prev, struct nouveau_channel *chan)
{
	struct nv84_fence_chan *fctx = chan->fence;
	u64 addr = fctx->vma->addr + nv84_fence_chid(prev) * 16;

	return fctx->base.sync32(chan, addr, fence->base.seqno);
}

static u32
nv84_fence_read(struct nouveau_channel *chan)
{
	struct nv84_fence_priv *priv = chan->cli->drm->fence;
	return nouveau_bo_rd32(priv->bo, nv84_fence_chid(chan) * 16/4);
}

static void
nv84_fence_context_del(struct nouveau_channel *chan)

Annotation

Implementation Notes