drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h

Extension

.h

Size

9196 bytes

Lines

220

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• engine/fifo.h
• core/enum.h

Detected Declarations

• struct nvkm_cctx
• struct nvkm_cgrp
• struct nvkm_chan
• struct nvkm_engn
• struct nvkm_memory
• struct nvkm_runl
• struct nvkm_runq
• struct nvkm_vctx
• struct nvkm_fifo_func
• struct nvkm_fifo_func_cgrp
• struct nvkm_fifo_func_chan

Annotated Snippet

struct nvkm_fifo_func {
	void (*dtor)(struct nvkm_fifo *);

	int (*chid_nr)(struct nvkm_fifo *);
	int (*chid_ctor)(struct nvkm_fifo *, int nr);
	int (*runq_nr)(struct nvkm_fifo *);
	int (*runl_ctor)(struct nvkm_fifo *);

	void (*init)(struct nvkm_fifo *);
	void (*init_pbdmas)(struct nvkm_fifo *, u32 mask);

	irqreturn_t (*intr)(struct nvkm_inth *);
	void (*intr_mmu_fault_unit)(struct nvkm_fifo *, int unit);
	void (*intr_ctxsw_timeout)(struct nvkm_fifo *, u32 engm);

	const struct nvkm_fifo_func_mmu_fault {
		void (*recover)(struct nvkm_fifo *, struct nvkm_fault_data *);
		const struct nvkm_enum *access;
		const struct nvkm_enum *engine;
		const struct nvkm_enum *reason;
		const struct nvkm_enum *hubclient;
		const struct nvkm_enum *gpcclient;
	} *mmu_fault;

	void (*pause)(struct nvkm_fifo *, unsigned long *);
	void (*start)(struct nvkm_fifo *, unsigned long *);

	int (*nonstall_ctor)(struct nvkm_fifo *);
	void (*nonstall_dtor)(struct nvkm_fifo *);
	const struct nvkm_event_func *nonstall;

	const struct nvkm_runl_func *runl;
	const struct nvkm_runq_func *runq;
	const struct nvkm_engn_func *engn;
	const struct nvkm_engn_func *engn_sw;
	const struct nvkm_engn_func *engn_ce;

	struct nvkm_fifo_func_cgrp {
		struct nvkm_sclass user;
		const struct nvkm_cgrp_func *func;
		bool force;
	} cgrp;

	struct nvkm_fifo_func_chan {
		struct nvkm_sclass user;
		const struct nvkm_chan_func *func;
	} chan;
};

int r535_fifo_new(const struct nvkm_fifo_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
		  struct nvkm_fifo **);
int nvkm_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
		   struct nvkm_fifo **);

int nv04_fifo_chid_ctor(struct nvkm_fifo *, int);
int nv04_fifo_runl_ctor(struct nvkm_fifo *);
void nv04_fifo_init(struct nvkm_fifo *);
irqreturn_t nv04_fifo_intr(struct nvkm_inth *);
void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *);
void nv04_fifo_start(struct nvkm_fifo *, unsigned long *);
extern const struct nvkm_runl_func nv04_runl;
extern const struct nvkm_engn_func nv04_engn;
extern const struct nvkm_cgrp_func nv04_cgrp;
extern const struct nvkm_chan_func_inst nv04_chan_inst;
extern const struct nvkm_chan_func_userd nv04_chan_userd;
void nv04_chan_ramfc_clear(struct nvkm_chan *);
void nv04_chan_start(struct nvkm_chan *);
void nv04_chan_stop(struct nvkm_chan *);
void nv04_eobj_ramht_del(struct nvkm_chan *, int);

int nv10_fifo_chid_nr(struct nvkm_fifo *);

int nv50_fifo_chid_nr(struct nvkm_fifo *);
int nv50_fifo_chid_ctor(struct nvkm_fifo *, int);
void nv50_fifo_init(struct nvkm_fifo *);
extern const struct nvkm_runl_func nv50_runl;
int nv50_runl_update(struct nvkm_runl *);
int nv50_runl_wait(struct nvkm_runl *);
extern const struct nvkm_engn_func nv50_engn_sw;
extern const struct nvkm_chan_func_inst nv50_chan_inst;
extern const struct nvkm_chan_func_userd nv50_chan_userd;
void nv50_chan_unbind(struct nvkm_chan *);
void nv50_chan_start(struct nvkm_chan *);
void nv50_chan_stop(struct nvkm_chan *);
void nv50_chan_preempt(struct nvkm_chan *);
int nv50_eobj_ramht_add(struct nvkm_engn *, struct nvkm_object *, struct nvkm_chan *);
void nv50_eobj_ramht_del(struct nvkm_chan *, int);

extern const struct nvkm_event_func g84_fifo_nonstall;
extern const struct nvkm_engn_func g84_engn;

Annotation

• Immediate include surface: `engine/fifo.h`, `core/enum.h`.
• Detected declarations: `struct nvkm_cctx`, `struct nvkm_cgrp`, `struct nvkm_chan`, `struct nvkm_engn`, `struct nvkm_memory`, `struct nvkm_runl`, `struct nvkm_runq`, `struct nvkm_vctx`, `struct nvkm_fifo_func`, `struct nvkm_fifo_func_cgrp`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.