drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
Extension
.c
Size
47111 bytes
Lines
1588
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (!atarget) {
			nvkm_warn(subdev, "missing alpha/beta mapping table\n");
			atarget = max_t(u32, gr->tpc_total * i / 32, 1);
		}

		while (atarget) {
			for (gpc = 0; atarget && gpc < gr->gpc_nr; gpc++) {
				if (abits[gpc] < gr->tpc_nr[gpc]) {
					abits[gpc]++;
					atarget--;
				}
			}
		}

		for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
			u32 bbits = gr->tpc_nr[gpc] - abits[gpc];
			amask |= ((1 << abits[gpc]) - 1) << (gpc * 8);
			bmask |= ((1 << bbits) - 1) << abits[gpc] << (gpc * 8);
		}

		nvkm_wr32(device, 0x406800 + (i * 0x20), amask);
		nvkm_wr32(device, 0x406c00 + (i * 0x20), bmask);
	}
}

void
gf100_grctx_generate_tpc_nr(struct gf100_gr *gr, int gpc)
{
	struct nvkm_device *device = gr->base.engine.subdev.device;
	nvkm_wr32(device, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]);
	nvkm_wr32(device, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]);
}

void
gf100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
{
	struct nvkm_device *device = gr->base.engine.subdev.device;
	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), sm);
	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x4e8), sm);
	nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm);
	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
}

void
gf100_grctx_generate_floorsweep(struct gf100_gr *gr)
{
	const struct gf100_grctx_func *func = gr->func->grctx;
	int sm;

	for (sm = 0; sm < gr->sm_nr; sm++) {
		func->sm_id(gr, gr->sm[sm].gpc, gr->sm[sm].tpc, sm);
		if (func->tpc_nr)
			func->tpc_nr(gr, gr->sm[sm].gpc);
	}

	gf100_gr_init_num_tpc_per_gpc(gr, false, true);
	if (!func->skip_pd_num_tpc_per_gpc)
		gf100_gr_init_num_tpc_per_gpc(gr, true, false);

	if (func->r4060a8)
		func->r4060a8(gr);

	func->rop_mapping(gr);

	if (func->alpha_beta_tables)
		func->alpha_beta_tables(gr);
	if (func->max_ways_evict)
		func->max_ways_evict(gr);
	if (func->dist_skip_table)
		func->dist_skip_table(gr);
	if (func->r406500)
		func->r406500(gr);
	if (func->gpc_tpc_nr)
		func->gpc_tpc_nr(gr);
	if (func->r419f78)
		func->r419f78(gr);
	if (func->tpc_mask)
		func->tpc_mask(gr);
	if (func->smid_config)
		func->smid_config(gr);
}

void
gf100_grctx_generate_main(struct gf100_gr_chan *chan)
{
	struct gf100_gr *gr = chan->gr;
	struct nvkm_device *device = gr->base.engine.subdev.device;
	const struct gf100_grctx_func *grctx = gr->func->grctx;
	u32 idle_timeout;

Annotation

Implementation Notes