drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c
Extension
.c
Size
5254 bytes
Lines
152
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include "ctxgf100.h"

#include <subdev/fb.h>

/*******************************************************************************
 * PGRAPH context implementation
 ******************************************************************************/

void
gp100_grctx_generate_pagepool(struct gf100_gr_chan *chan, u64 addr)
{
	gf100_grctx_patch_wr32(chan, 0x40800c, addr >> 8);
	gf100_grctx_patch_wr32(chan, 0x408010, 0x8007d800);
	gf100_grctx_patch_wr32(chan, 0x419004, addr >> 8);
	gf100_grctx_patch_wr32(chan, 0x419008, 0x00000000);
}

static void
gp100_grctx_generate_attrib(struct gf100_gr_chan *chan)
{
	struct gf100_gr *gr = chan->gr;
	const struct gf100_grctx_func *grctx = gr->func->grctx;
	const u32  alpha = grctx->alpha_nr;
	const u32 attrib = grctx->attrib_nr;
	const int max_batches = 0xffff;
	u32 size = grctx->alpha_nr_max * gr->tpc_total;
	u32 ao = 0;
	u32 bo = ao + size;
	int gpc, ppc, n = 0;

	gf100_grctx_patch_wr32(chan, 0x405830, attrib);
	gf100_grctx_patch_wr32(chan, 0x40585c, alpha);
	gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);

	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
		for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) {
			const u32 as =  alpha * gr->ppc_tpc_nr[gpc][ppc];
			const u32 bs = attrib * gr->ppc_tpc_max;
			const u32 u = 0x418ea0 + (n * 0x04);
			const u32 o = PPC_UNIT(gpc, ppc, 0);

			if (!(gr->ppc_mask[gpc] & (1 << ppc)))
				continue;

			gf100_grctx_patch_wr32(chan, o + 0xc0, bs);
			gf100_grctx_patch_wr32(chan, o + 0xf4, bo);
			gf100_grctx_patch_wr32(chan, o + 0xf0, bs);
			bo += grctx->attrib_nr_max * gr->ppc_tpc_max;
			gf100_grctx_patch_wr32(chan, o + 0xe4, as);
			gf100_grctx_patch_wr32(chan, o + 0xf8, ao);
			ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
			gf100_grctx_patch_wr32(chan, u, bs);
		}
	}

	gf100_grctx_patch_wr32(chan, 0x418eec, 0x00000000);
	gf100_grctx_patch_wr32(chan, 0x41befc, 0x00000000);
}

void
gp100_grctx_generate_attrib_cb(struct gf100_gr_chan *chan, u64 addr, u32 size)
{
	gm107_grctx_generate_attrib_cb(chan, addr, size);

	gf100_grctx_patch_wr32(chan, 0x419b00, 0x00000000 | addr >> 12);
	gf100_grctx_patch_wr32(chan, 0x419b04, 0x80000000 | size >> 7);
}

static u32
gp100_grctx_generate_attrib_cb_size(struct gf100_gr *gr)
{
	const struct gf100_grctx_func *grctx = gr->func->grctx;
	u32 size = grctx->alpha_nr_max * gr->tpc_total;
	int gpc;

	for (gpc = 0; gpc < gr->gpc_nr; gpc++)
		size += grctx->attrib_nr_max * gr->func->ppc_nr * gr->ppc_tpc_max;

	return ((size * 0x20) + 128) & ~127;
}

void
gp100_grctx_generate_smid_config(struct gf100_gr *gr)
{
	struct nvkm_device *device = gr->base.engine.subdev.device;
	const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
	u32 dist[TPC_MAX / 4] = {}, gpcs[16] = {};
	u8  sm, i;

	for (sm = 0; sm < gr->sm_nr; sm++) {

Annotation

Implementation Notes