drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc
Extension
.fuc
Size
16889 bytes
Lines
700
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: drivers/gpu
Status
atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifdef INCLUDE_DATA
hub_mmio_list_head:	.b32 #hub_mmio_list_base
hub_mmio_list_tail:	.b32 #hub_mmio_list_next

gpc_count:		.b32 0
rop_count:		.b32 0
cmd_queue:		queue_init

ctx_current:		.b32 0

.align 256
chan_data:
chan_mmio_count:	.b32 0
chan_mmio_address:	.b32 0

.align 256
xfer_data: 		.skip 256

hub_mmio_list_base:
.b32 0x0417e91c // 0x17e91c, 2
hub_mmio_list_next:
#endif

#ifdef INCLUDE_CODE
// reports an exception to the host
//
// In: $r15 error code (see os.h)
//
error:
	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15)
	mov $r15 1
	nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r15)
	ret

// HUB fuc initialisation, executed by triggering ucode start, will
// fall through to main loop after completion.
//
// Output:
//   CC_SCRATCH[0]:
//	     31:31: set to signal completion
//   CC_SCRATCH[1]:
//	      31:0: total PGRAPH context size
//
init:
	clear b32 $r0
	mov $xdbase $r0

	// setup stack
	nv_iord($r1, NV_PGRAPH_FECS_CAPS, 0)
	extr $r1 $r1 9:17
	shl b32 $r1 8
	mov $sp $r1

	// enable fifo access
	mov $r2 NV_PGRAPH_FECS_ACCESS_FIFO
	nv_iowr(NV_PGRAPH_FECS_ACCESS, 0, $r2)

	// setup i0 handler, and route all interrupts to it
	mov $r1 #ih
	mov $iv0 $r1

	clear b32 $r2
	nv_iowr(NV_PGRAPH_FECS_INTR_ROUTE, 0, $r2)

	// route HUB_CHSW_PULSE to fuc interrupt 8
	mov $r2 0x2003		// { HUB_CHSW_PULSE, ZERO } -> intr 8
	nv_iowr(NV_PGRAPH_FECS_IROUTE, 0, $r2)

	// not sure what these are, route them because NVIDIA does, and
	// the IRQ handler will signal the host if we ever get one.. we

Annotation

Implementation Notes