drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc
Extension: .fuc
Size: 14839 bytes
Lines: 262
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: drivers/gpu
Status: atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

os.h

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#include "os.h"

#define GF100 0xc0
#define GF117 0xd7
#define GK100 0xe0
#define GK110 0xf0
#define GK208 0x108
#define GM107 0x117

#define NV_PGRAPH_TRAPPED_ADDR                                         0x400704
#define NV_PGRAPH_TRAPPED_DATA_LO                                      0x400708
#define NV_PGRAPH_TRAPPED_DATA_HI                                      0x40070c

#define NV_PGRAPH_FE_OBJECT_TABLE(n)                        ((n) * 4 + 0x400700)

#define NV_PGRAPH_FECS_INTR_ACK                                        0x409004
#define NV_PGRAPH_FECS_INTR                                            0x409008
#define NV_PGRAPH_FECS_INTR_FWMTHD                                   0x00000400
#define NV_PGRAPH_FECS_INTR_CHSW                                     0x00000100
#define NV_PGRAPH_FECS_INTR_FIFO                                     0x00000004
#define NV_PGRAPH_FECS_INTR_MODE                                       0x40900c
#define NV_PGRAPH_FECS_INTR_MODE_FIFO                                0x00000004
#define NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL                          0x00000004
#define NV_PGRAPH_FECS_INTR_MODE_FIFO_EDGE                           0x00000000
#define NV_PGRAPH_FECS_INTR_EN_SET                                     0x409010
#define NV_PGRAPH_FECS_INTR_EN_SET_FIFO                              0x00000004
#define NV_PGRAPH_FECS_INTR_ROUTE                                      0x40901c
#define NV_PGRAPH_FECS_ACCESS                                          0x409048
#define NV_PGRAPH_FECS_ACCESS_FIFO                                   0x00000002
#define NV_PGRAPH_FECS_FIFO_DATA                                       0x409064
#define NV_PGRAPH_FECS_FIFO_CMD                                        0x409068
#define NV_PGRAPH_FECS_FIFO_ACK                                        0x409074
#define NV_PGRAPH_FECS_CAPS                                            0x409108
#define NV_PGRAPH_FECS_SIGNAL                                          0x409400
#define NV_PGRAPH_FECS_IROUTE                                          0x409404
#define NV_PGRAPH_FECS_BAR_MASK0                                       0x40940c
#define NV_PGRAPH_FECS_BAR_MASK1                                       0x409410
#define NV_PGRAPH_FECS_BAR                                             0x409414
#define NV_PGRAPH_FECS_BAR_SET                                         0x409418
#define NV_PGRAPH_FECS_RED_SWITCH                                      0x409614
#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP                         0x00000400
#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC                         0x00000200
#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN                        0x00000100
#define NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP                          0x00000040
#define NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC                          0x00000020
#define NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN                         0x00000010
#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_GPC                          0x00000002
#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_MAIN                         0x00000001
#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE                               0x409700
#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE                               0x409704
#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT                                0x40974c
#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE                               0x409700
#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE                               0x409704
#define NV_PGRAPH_FECS_MMCTX_BASE                                      0x409710
#define NV_PGRAPH_FECS_MMCTX_CTRL                                      0x409714
#define NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE                              0x409718
#define NV_PGRAPH_FECS_MMCTX_MULTI_MASK                                0x40971c
#define NV_PGRAPH_FECS_MMCTX_QUEUE                                     0x409720
#define NV_PGRAPH_FECS_MMIO_BASE                                       0x409724
#define NV_PGRAPH_FECS_MMIO_CTRL                                       0x409728
#define NV_PGRAPH_FECS_MMIO_CTRL_BASE_ENABLE                         0x00000001
#define NV_PGRAPH_FECS_MMIO_RDVAL                                      0x40972c
#define NV_PGRAPH_FECS_MMIO_WRVAL                                      0x409730
#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT                                0x40974c
#if CHIPSET < GK110
#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n)                    ((n) * 4 + 0x409800)
#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n)                    ((n) * 4 + 0x409820)
#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n)                    ((n) * 4 + 0x409840)
#define NV_PGRAPH_FECS_UNK86C                                          0x40986c
#else

Annotation

Immediate include surface: `os.h`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.