drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c- Extension
.c- Size
- 5130 bytes
- Lines
- 162
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
gf100.hctxgf100.hnvif/class.h
Detected Declarations
function gf104_gr_new
Annotated Snippet
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
const struct gf100_gr_init
gf104_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00002834 },
{ 0x405908, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf104_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf104_gr_init_pe_0[] = {
{ 0x41980c, 3, 0x04, 0x00000000 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc5 },
{ 0x419850, 4, 0x04, 0x00000000 },
{ 0x419880, 1, 0x04, 0x00000002 },
{}
};
const struct gf100_gr_init
gf104_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x00001100 },
{ 0x419eac, 1, 0x04, 0x11100702 },
{ 0x419eb0, 1, 0x04, 0x00000003 },
{ 0x419eb4, 4, 0x04, 0x00000000 },
{ 0x419ec8, 1, 0x04, 0x0e063818 },
{ 0x419ecc, 1, 0x04, 0x0e060e06 },
{ 0x419ed0, 1, 0x04, 0x00003818 },
{ 0x419ed4, 1, 0x04, 0x011104f1 },
{ 0x419edc, 1, 0x04, 0x00000000 },
{ 0x419f00, 1, 0x04, 0x00000000 },
{ 0x419f2c, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gf104_gr_pack_mmio[] = {
{ gf100_gr_init_main_0 },
{ gf100_gr_init_fe_0 },
{ gf100_gr_init_pri_0 },
{ gf100_gr_init_rstr2d_0 },
{ gf100_gr_init_pd_0 },
{ gf104_gr_init_ds_0 },
{ gf100_gr_init_scc_0 },
{ gf100_gr_init_prop_0 },
{ gf100_gr_init_gpc_unk_0 },
{ gf100_gr_init_setup_0 },
{ gf100_gr_init_crstr_0 },
{ gf100_gr_init_setup_1 },
{ gf100_gr_init_zcull_0 },
{ gf100_gr_init_gpm_0 },
{ gf100_gr_init_gpc_unk_1 },
{ gf100_gr_init_gcc_0 },
{ gf100_gr_init_tpccs_0 },
{ gf104_gr_init_tex_0 },
{ gf104_gr_init_pe_0 },
{ gf100_gr_init_l1c_0 },
{ gf100_gr_init_wwdx_0 },
{ gf100_gr_init_tpccs_1 },
{ gf100_gr_init_mpc_0 },
{ gf104_gr_init_sm_0 },
{ gf100_gr_init_be_0 },
{ gf100_gr_init_fe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
Annotation
- Immediate include surface: `gf100.h`, `ctxgf100.h`, `nvif/class.h`.
- Detected declarations: `function gf104_gr_new`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.