drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c- Extension
.c- Size
- 39986 bytes
- Lines
- 1427
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
priv.hregs.hcore/client.hcore/gpuobj.hengine/fifo.hengine/fifo/chan.hsubdev/instmem.hsubdev/timer.h
Detected Declarations
struct nv04_grstruct nv04_gr_chanfunction nv04_gr_set_ctx1function nv04_gr_set_ctx_valfunction nv04_gr_mthd_set_operationfunction nv04_gr_mthd_surf3d_clip_hfunction nv04_gr_mthd_surf3d_clip_vfunction nv04_gr_mthd_bind_classfunction nv04_gr_mthd_bind_surf2dfunction nv04_gr_mthd_bind_surf2d_swzsurffunction nv01_gr_mthd_bind_pattfunction nv04_gr_mthd_bind_pattfunction nv04_gr_mthd_bind_ropfunction nv04_gr_mthd_bind_beta1function nv04_gr_mthd_bind_beta4function nv04_gr_mthd_bind_surf_dstfunction nv04_gr_mthd_bind_surf_srcfunction nv04_gr_mthd_bind_surf_colorfunction nv04_gr_mthd_bind_surf_zetafunction nv01_gr_mthd_bind_clipfunction nv01_gr_mthd_bind_chromafunction nv03_gr_mthd_gdifunction nv04_gr_mthd_gdifunction nv01_gr_mthd_blitfunction nv04_gr_mthd_blitfunction nv04_gr_mthd_iifcfunction nv01_gr_mthd_ifcfunction nv04_gr_mthd_ifcfunction nv03_gr_mthd_sifcfunction nv04_gr_mthd_sifcfunction nv03_gr_mthd_sifmfunction nv04_gr_mthd_sifmfunction nv04_gr_mthd_surf3dfunction nv03_gr_mthd_ttrifunction nv01_gr_mthd_primfunction nv04_gr_mthd_primfunction nv04_gr_mthdfunction nv04_gr_object_bindfunction nv04_gr_channelfunction nv04_gr_load_contextfunction nv04_gr_unload_contextfunction nv04_gr_context_switchfunction nv04_gr_chan_dtorfunction nv04_gr_chan_finifunction nv04_gr_chan_newfunction nv04_gr_idlefunction nv04_gr_intrfunction nv04_gr_init
Annotated Snippet
struct nv04_gr {
struct nvkm_gr base;
struct nv04_gr_chan *chan[16];
spinlock_t lock;
};
#define nv04_gr_chan(p) container_of((p), struct nv04_gr_chan, object)
struct nv04_gr_chan {
struct nvkm_object object;
struct nv04_gr *gr;
int chid;
u32 nv04[ARRAY_SIZE(nv04_gr_ctx_regs)];
};
/*******************************************************************************
* Graphics object classes
******************************************************************************/
/*
* Software methods, why they are needed, and how they all work:
*
* NV04 and NV05 keep most of the state in PGRAPH context itself, but some
* 2d engine settings are kept inside the grobjs themselves. The grobjs are
* 3 words long on both. grobj format on NV04 is:
*
* word 0:
* - bits 0-7: class
* - bit 12: color key active
* - bit 13: clip rect active
* - bit 14: if set, destination surface is swizzled and taken from buffer 5
* [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
* from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
* NV03_CONTEXT_SURFACE_DST].
* - bits 15-17: 2d operation [aka patch config]
* - bit 24: patch valid [enables rendering using this object]
* - bit 25: surf3d valid [for tex_tri and multitex_tri only]
* word 1:
* - bits 0-1: mono format
* - bits 8-13: color format
* - bits 16-31: DMA_NOTIFY instance
* word 2:
* - bits 0-15: DMA_A instance
* - bits 16-31: DMA_B instance
*
* On NV05 it's:
*
* word 0:
* - bits 0-7: class
* - bit 12: color key active
* - bit 13: clip rect active
* - bit 14: if set, destination surface is swizzled and taken from buffer 5
* [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
* from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
* NV03_CONTEXT_SURFACE_DST].
* - bits 15-17: 2d operation [aka patch config]
* - bits 20-22: dither mode
* - bit 24: patch valid [enables rendering using this object]
* - bit 25: surface_dst/surface_color/surf2d/surf3d valid
* - bit 26: surface_src/surface_zeta valid
* - bit 27: pattern valid
* - bit 28: rop valid
* - bit 29: beta1 valid
* - bit 30: beta4 valid
* word 1:
* - bits 0-1: mono format
* - bits 8-13: color format
* - bits 16-31: DMA_NOTIFY instance
* word 2:
* - bits 0-15: DMA_A instance
* - bits 16-31: DMA_B instance
*
* NV05 will set/unset the relevant valid bits when you poke the relevant
* object-binding methods with object of the proper type, or with the NULL
* type. It'll only allow rendering using the grobj if all needed objects
* are bound. The needed set of objects depends on selected operation: for
* example rop object is needed by ROP_AND, but not by SRCCOPY_AND.
*
* NV04 doesn't have these methods implemented at all, and doesn't have the
* relevant bits in grobj. Instead, it'll allow rendering whenever bit 24
* is set. So we have to emulate them in software, internally keeping the
* same bits as NV05 does. Since grobjs are aligned to 16 bytes on nv04,
* but the last word isn't actually used for anything, we abuse it for this
* purpose.
*
* Actually, NV05 can optionally check bit 24 too, but we disable this since
* there's no use for it.
*
* For unknown reasons, NV04 implements surf3d binding in hardware as an
* exception. Also for unknown reasons, NV04 doesn't implement the clipping
Annotation
- Immediate include surface: `priv.h`, `regs.h`, `core/client.h`, `core/gpuobj.h`, `engine/fifo.h`, `engine/fifo/chan.h`, `subdev/instmem.h`, `subdev/timer.h`.
- Detected declarations: `struct nv04_gr`, `struct nv04_gr_chan`, `function nv04_gr_set_ctx1`, `function nv04_gr_set_ctx_val`, `function nv04_gr_mthd_set_operation`, `function nv04_gr_mthd_surf3d_clip_h`, `function nv04_gr_mthd_surf3d_clip_v`, `function nv04_gr_mthd_bind_class`, `function nv04_gr_mthd_bind_surf2d`, `function nv04_gr_mthd_bind_surf2d_swzsurf`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.